Very Massive Hardware Merge Sorter
Very Massive Hardware Merge Sorter
复制标题
非常庞大的硬件合并排序器
DOI：
10.1109/fpt.2018.00023
复制
发表时间：
2018
期刊：
影响因子：
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通讯作者：
Kenji Kise
中科院分区：
文献类型：
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作者：
M. Saitoh;Kenji Kise
MMS硬件归并排序器存在记录绑定问题，即具有相同键的记录会导致该问题。MMS通过比较记录的关键字段和卫星数据字段来确定两个记录是否交换的低效方案解决了这个问题。我们提出了一个高性能的硬件合并排序器（VMS），采用了一个有效的解决方案，比较只是关键字段的问题。文中还给出了VMS的具体电路，并对电路进行了优化。我们实现和评估VMS上的Virtex-7 FPGA。评估结果表明，我们提出的合并排序器需要更少的硬件资源，并实现1.44倍更好的吞吐量比MMS时，使用大记录。
The state-of-the-art hardware merge sorter called MMS has the tie-record issue that the records having the same key can cause the problem. MMS solves this issue by inefficient scheme comparing both key and satellite data fields of records to determine whether two records are swapped or not. We propose a high-performance hardware merge sorter (VMS) which adopts an efficient solution to the issue comparing just key fields. We also present the detailed circuit of VMS that adopts some implementation optimizations. We implement and evaluate VMS on a Virtex-7 FPGA. The evaluation results show that our proposed merge sorter requires fewer hardware resources and achieves 1.44x better throughput than MMS when large records are used.