Set-Triggered-Parallel-Reset Memristor Logic for High-Density Heterogeneous-Integration Friendly Normally Off Applications
Set-Triggered-Parallel-Reset Memristor Logic for High-Density Heterogeneous-Integration Friendly Normally Off Applications
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DOI：
10.1109/tcsii.2014.2362713
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发表时间：
2015
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影响因子：
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通讯作者：
Meng-Fan Chang;Shu-Meng Yang;Chia-Chen Kuo;T. Yang;Che-Ju Yeh;Tun-Fei Chien;Li-Yue Huang;S. Sheu;P. Tseng;Yu-Sheng Chen;Frederick T. Chen;T. Ku;M. Tsai;M. Kao
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文献类型：
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作者：
Meng-Fan Chang;Shu-Meng Yang;Chia-Chen Kuo;T. Yang;Che-Ju Yeh;Tun-Fei Chien;Li-Yue Huang;S. Sheu;P. Tseng;Yu-Sheng Chen;Frederick T. Chen;T. Ku;M. Tsai;M. Kao
忆阻器器件有望成为使用不同技术的非高速、常关式应用的高密度计算逻辑。本简介提出了一种基于线后端双极型忆阻器器件的设置触发并行复位忆阻器逻辑(STPR-ML)，以减少面积开销并提高与标准和非标准CMOS工艺的兼容性。所提出的STPR-ML有两个子集：具有和不具有非易失性存储能力。文中还提出了STPR-ML的两种物理结构：二维和三维。为了验证STPR-ML中使用的NAND、NOR和XOR门的功能，采用了一种使用二维HfOx忆阻器器件的测试芯片。与具有四个或更多输入的CMOS逻辑门相比，所提出的STPR-ML的面积减少了2~8倍。
Memristor devices are promising as high-density computing logic for non-high-speed normally off applications using heterogeneous technologies. This brief proposes a settriggered-parallel-reset memristor logic (STPR-ML)-based on back-end-of-line-based bipolar-type memristor devices to reduce the area overhead and increase compatibility with standard and nonstandard CMOS processes. The proposed STPR-ML has two subsets: with and without nonvolatile storage capability. Two types of physical structures are also proposed for STPR-ML: 2-D and 3-D. A test chip using 2-D HfOx memristor devices was fabricated using a CMOS process to confirm the functionality of the NAND, NOR, and XOR gates used in STPR-ML. The proposed STPR-ML achieves a 2 ~ 8× reduction in area compared with CMOS logic gates with four or more inputs.