Ultralow-Noise Organic Transistors Based on Polymeric Gate Dielectrics with Self-Assembled Modifiers
Ultralow-Noise Organic Transistors Based on Polymeric Gate Dielectrics with Self-Assembled Modifiers
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基于具有自组装改性剂的聚合物栅极电介质的超低噪声有机晶体管
DOI:
10.1021/acsami.9b13056
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发表时间:
2019
影响因子:
9.5
通讯作者:
Sekitani Tsuyoshi
中科院分区:
文献类型:
--
作者:
Kondo Masaya;Uemura Takafumi;Ishiwari Fumitaka;Kajitani Takashi;Shoji Yoshiaki;Morita Masato;Namba Naoko;Inoue Yumi;Noda Yuki;Araki Teppei;Fukushima Takanori;Sekitani Tsuyoshi
In this study, ultralow 1/fnoise organic thin-film transistors (OTFTs) based on parylene gate dielectrics modified with triptycene (Trip) modifiers were fabricated. The fabricated OTFTs showed the lowest 1/fnoise level among those of previously reported OTFTs. It is well known that 1/fnoise causes degradation of signal integrity in analog and digital circuits. However, conventional OTFTs still possess high 1/fnoise levels, and the factors that strongly affect 1/fnoise are still ambiguous. In this work, the effect of gate dielectric surface on 1/fnoise was investigated. First, by comparing OTFTs composed of various channel lengths, we revealed that contact resistance did not affect 1/fnoise. Second, we compared parylene OTFTs with and without a self-assembled Trip modifier layer in terms of 1/fnoise and trap density of states (Trap DOS). The experiments revealed that a specific Trip modifier layer suppresses the shallow Trap DOS in the OTFTs, leading to a low 1/fnoise. Moreover, the 1/fnoise level and Trap DOS of various kinds of OTFTs were comprehensively compared, which highlighted that the 1/fnoise of OTFTs strongly depends on the gate dielectric surface. Finally, detailed analysis of the gate dielectric interface led us to conclude that the disorder of gate dielectrics and the crystalline quality of semiconductor films are related to shallow Trap DOS, which correlates with 1/fnoise.