A 22.2-43 GHz Gate-Drain Mutually Induced Feedback Low Noise Amplifier in 28-nm CMOS
A 22.2-43 GHz Gate-Drain Mutually Induced Feedback Low Noise Amplifier in 28-nm CMOS
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采用 28-nm CMOS 封装的 22.2-43 GHz 栅漏互感反馈低噪声放大器
DOI：
10.1109/rfic51843.2021.9490469
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发表时间：
2021
期刊：
影响因子：
--
通讯作者：
K. Entesari
中科院分区：
文献类型：
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作者：
A. Ershadi;S. Palermo;K. Entesari
提出了一种新的毫米波低噪声放大器（LNA）结构，能够在大带宽上同时实现功率和噪声匹配。研究表明，通过将一对连接在晶体管栅极和漏极的电感进行磁耦合，产生从漏极电流到栅极的（串联-串联）反馈路径，其：1）增加晶体管输入阻抗幅度，2）产生可被控制用于功率匹配的实阻抗部分，以及3）使最佳噪声源阻抗接近最佳功率匹配阻抗。原型采用TSMC 28 nm体CMOS工艺制作。实测芯片工作频率范围为22.2至43 GHz，峰值增益为21 dB，最小NF为3.5 dB，平均IIP 3为−3 dBm。
A novel mm-wave low-noise-amplifier (LNA) architecture capable of achieving simultaneous power and noise matching over a large bandwidth is proposed. It is shown that by magnetically coupling a pair of inductors connected at the gate and drain of a transistor, a loss-less (series-series) feedback path from the drain-current to the gate is generated which: 1) Increases the transistor input impedance magnitude, 2) generates a real-impedance part which can be controlled for power-matching, and 3) brings the optimum noise source impedance close to the optimum power matching impedance. The prototype is fabricated in TSMC 28-nm bulk CMOS process. The measured chip is functional from 22.2 to 43 GHz, while providing 21 dB of peak gain, minimum NF of 3.5 dB, and an average IIP3 of −3 dBm.