IOMMU: strategies for mitigating the IOTLB bottleneck
IOMMU: strategies for mitigating the IOTLB bottleneck
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DOI：
10.1007/978-3-642-24322-6_22
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发表时间：
2010-06
期刊：
影响因子：
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通讯作者：
Nadav Amit;Muli Ben-Yehuda;Ben-Ami Yassour
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文献类型：
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作者：
Nadav Amit;Muli Ben-Yehuda;Ben-Ami Yassour
输入/输出存储器管理单元(IOMMU)最近被引入到主流计算机体系结构中，因为Intel和AMD都将IOMMU添加到他们的芯片组中。IOMMU通过使系统软件能够控制I/O设备可以访问物理内存的哪些区域来提供针对I/O设备的内存保护。然而，由于所需的地址解析和验证，这种保护会导致额外的直接存储器访问(DMA)开销。IOMMU包括一个输入/输出转换后备缓冲器(IOTLB)来加速地址解析，但每一次IOTLB高速缓存未命中都会导致DMA延迟的大幅增加和DMA密集型工作负载的性能下降。在本文中，我们首先演示IOTLB缓存未命中对工作负载性能的潜在负面影响。然后，我们提出了系统软件和硬件方面的改进，以降低IOTLB未命中率和加快地址解析。这些增强功能可将常见I/O密集型工作负载的IOTLB未命中率降低60%以上。
Theinput/output memory management unit(IOMMU) was recently introduced into mainstream computer architecture when both Intel and AMD added IOMMUs to their chip-sets. An IOMMU provides memory protection from I/O devices by enabling system software to control which areas of physical memory an I/O device may access. However, this protection incurs additionaldirect memory access(DMA) overhead due to the required address resolution and validation.IOMMUs include aninput/output translation lookaside buffer(IOTLB) to speed-up address resolution, but still every IOTLB cache-miss causes a substantial increase in DMA latency and performance degradation of DMA-intensive workloads. In this paper we first demonstrate the potential negative impact of IOTLB cache-misses on workload performance. We then propose both system software and hardware enhancements to reduce IOTLB miss rate and accelerate address resolution. These enhancements can lead to a reduction of over 60% in IOTLB miss-rate for common I/O intensive workloads.