A 15mW 3.6GS/s CT-ΔΣ ADC with 36MHz bandwidth and 83dB DR in 90nm CMOS
A 15mW 3.6GS/s CT-ΔΣ ADC with 36MHz bandwidth and 83dB DR in 90nm CMOS
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采用 90nm CMOS 封装、具有 36MHz 带宽和 83dB DR 的 15mW 3.6GS/s CT-ΔΣ ADC
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发表时间：
2012
期刊：
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通讯作者：
S. Pavan
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作者：
Pradeep Shettigar;S. Pavan
我们提出的设计技术能够实现多gb /s速度的节能单比特CT-ΔΣ adc。FIR DAC[1]用于降低对时钟抖动的灵敏度和放松环路滤波器线性度。大部分模拟路径补偿调制器为FIR DAC引入的延迟。CTDSM样品在3.6GS/S下，在36MHz BW下具有83dB DR，在90nm CMOS下占地0.12mm2。从1.2V电源中损耗15mW，从而实现72.8fJ/级的FoMSNDR，这是对带宽大于20MHz的转换器的改进。
We propose design techniques that enable the realization of power-efficient single-bit CT-ΔΣ ADCs at multi-Gb/s speeds. An FIR DAC [1 ] is used to reduce sensitivity to clock jitter and relax loop filter linearity. A mostly analog path compensates the modulator for the delay introduced by the FIR DAC. The CTDSM samples at 3.6GS/S, has 83dB DR in 36MHz BW, and occupies 0.12mm2 in 90nm CMOS. Dissipating 15mW from a 1.2V supply, it thereby achieves an FoMSNDR of 72.8fJ/level, which is an improvement over the state of the art for converters with bandwidths greater than 20MHz.