Multi-level logic minimization based on minimal support and its application to the minimization of look-up table type FPGAs
Multi-level logic minimization based on minimal support and its application to the minimization of look-up table type FPGAs
复制标题
基于最小支持的多级逻辑最小化及其在查表型FPGA最小化中的应用
DOI：
10.1109/iccad.1991.185332
复制
发表时间：
1991
期刊：
影响因子：
--
通讯作者：
Y. Matsunaga
中科院分区：
文献类型：
--
作者：
M. Fujita;Y. Matsunaga
本文提出了一种特别适用于查找表型FPGA（现场可编程门阵列）最小化的多级逻辑最小化方法。给定一组要最小化的节点，首先通过应用函数约简来计算为给定节点构造函数所需的支撑集。函数归约过程保证了每个节点都能得到最小支持度。然后对要极小化的节点集建立覆盖表，从而得到覆盖给定要极小化的节点集的所有函数的最小支集。结合MIS2.1标准脚本和布尔重替换极小化器，给出了ISCAS组合基准电路的初步实现及其结果，并验证了所提方法的有效性. <<ETX>>
The authors present a method for multilevel logic minimization which is particularly suitable for the minimization of look-up table type FPGAs (field programmable gate arrays). Given a set of nodes to be minimized, one first calculates sets of supports which are necessary to construct the functions for the given nodes by applying functional reduction. The functional reduction process guarantees that one can get the minimal support for each node. One then makes a covering table for the set of nodes to be minimized so that one can get the minimal supports to cover all the functions for the given set of nodes to be minimized. The authors present a preliminary implementation and its results for ISCAS combinational benchmark circuits combined with MIS2.1 standard script and a Boolean resubstitution minimizer, and show the effectiveness of the presented method.<<ETX>>