Checking for Electrical Level Security Threats in Bitstreams for Multi-tenant FPGAs
Checking for Electrical Level Security Threats in Bitstreams for Multi-tenant FPGAs
复制标题
检查多租户 FPGA 比特流中的电气级安全威胁
DOI：
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发表时间：
2018
期刊：
影响因子：
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通讯作者：
M. Tahoori
中科院分区：
文献类型：
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作者：
Dennis R. E. Gnad;Sascha Rapp;Jonas Krautter;M. Tahoori
多租户FPGA，其中第三方可以部分访问FPGA结构，是云和可重配置SoC中的一个上升趋势。正如最近的研究所示，这会导致FPGA中出现新类型的攻击。这些攻击可以通过常见的电力输送网络在电气层面上操作，使其很难隔离。因此，可以利用软件控制的FPGA配置插入硬件木马，影响整个系统的安全性。这些攻击可以分为故障攻击和侧信道攻击，以主动操纵系统或悄悄提取秘密信息。在本文中，我们展示了针对这些基于电压波动的攻击的对策的第一次尝试，通过分析FPGA比特流的恶意逻辑，基本上实现了FPGA防病毒。我们提供了一种方法来检查潜在的恶意结构的比特流，通过扩展商业和开源工具的组合。
Multi-tenant FPGAs, in which 3rd parties have partial access to the FPGA fabric, are a rising usage trend in cloud and reconfigurable SoCs. This gives rise to new types of attacks in FPGAs, as shown in recent studies. These attacks can operate on the electrical level through the common power delivery network, making them very hard to isolate. Thus, software-controlled FPGA configuration can be exploited to insert hardware trojans, impacting the security of the entire system. The attacks can be separated into fault and side-channel attacks to either actively manipulate a system or quietly extract secret information. In this paper, we show the first attempt of countermeasures against these voltage fluctuation based attacks, by analyzing FPGA bitstreams for malicious logic, basically implementing an FPGA antivirus. We provide a way to check bitstreams for potentially malicious structures, by extending a combination of commercial and open-source tools.