Verification of Threshold Voltage Variation of Scaled Transistors with Ultralarge-Scale Device Matrix Array Test Element Group
Verification of Threshold Voltage Variation of Scaled Transistors with Ultralarge-Scale Device Matrix Array Test Element Group
复制标题
使用超大规模器件矩阵阵列测试元件组验证按比例缩小的晶体管的阈值电压变化
DOI:
10.1143/jjap.48.124505
复制
发表时间:
2009
影响因子:
1.5
通讯作者:
T. Hiramoto
中科院分区:
文献类型:
--
作者:
T. Tsunomura;A. Nishida;T. Hiramoto
Randomness of threshold voltage (VT) variations of negative channel field effect transistors (NFETs) and positive channel field effect transistors (PFETs) in the 65 nm technology is precisely examined. For this purpose, an ultralarge-scale device matrix array test element group (DMA-TEG) that contains 1 million single-size metal–oxide–semiconductor field-effect transistors (MOSFETs) has been designed and fabricated, and a very rapid measurement system has been developed. By evaluating VT of a very large number of MOSFETs, VT variation can be precisely evaluated. This rapid measurement is achieved by parallel address signal input, optimization of the measurement program, and 4-chip parallel measurements. The measured VT variations are decomposed into random and systematic components. The results reveal that the random component is overwhelmingly dominant in the VT variations in the 65 nm technology and that the VT variations exhibit a normal distribution up to ±5σ.