A fast-locking wide-range all-digital delay-locked loop with a starting SAR-bit prediction mechanism
A fast-locking wide-range all-digital delay-locked loop with a starting SAR-bit prediction mechanism
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DOI：
10.1109/vldi-dat.2013.6533870
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发表时间：
2013-04
期刊：
影响因子：
--
通讯作者：
Chia-Yu Yao;Yung-Hsiang Ho
中科院分区：
文献类型：
--
作者：
Chia-Yu Yao;Yung-Hsiang Ho
This paper presents an 11-bit all-digital delay-locked loop (ADDLL) with a starting SAR-bit prediction (SSARBP) mechanism. The proposed circuit possesses a wide-operating range such that it can serve as a de-skew buffer for the clock signal. With the proposed SSARBP mechanism, the ADDLL can achieve fast lock and can eliminate the harmonic lock. In the beginning of a SSARBP cycle, the circuit estimates the current delay of the digital-controlled delay line (DCDL). We then predict a suitable SAR starting bit to shorten the lock time. The ADDLL chip is designed using TSMC's 0.18 μm CMOS cell library. The post-simulation results show that the proposed circuit can operate from 66 MHz to 1 GHz. In the low frequency band, the lock time is within 17-23 clock cycles. In the high frequency band, the lock time is within 17-32 clock cycles. The power consumption of the chip is estimated to be 22 mW at 1.8-V supply voltage and 1-GHz clock frequency.
