Dependence of Device Structures on Latchup Immunity in a High-Voltage 40-V CMOS Process With Drain-Extended MOSFETs
Dependence of Device Structures on Latchup Immunity in a High-Voltage 40-V CMOS Process With Drain-Extended MOSFETs
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DOI：
10.1109/ted.2007.892013
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发表时间：
2007-04
影响因子：
3.1
通讯作者：
Sheng-Fu Hsu;M. Ker
中科院分区：
文献类型：
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作者：
Sheng-Fu Hsu;M. Ker
在具有漏极扩展 MOS (DEMOS) 晶体管的 0.25μm 高压 (HV) 40-V CMOS 工艺中，器件结构对闩锁抗扰度的依赖性已通过硅测试芯片进行了验证，并通过器件仿真进行了研究。还研究了阳极到阴极间距和保护环宽度等布局参数，以找出它们对闩锁抗扰度的影响。事实证明，具有特定隔离器件结构的漏极扩展NMOS可以大大增强抗闩锁能力。所提出的测试结构和仿真方法可用于提取安全且紧凑的设计规则，以防止 HV CMOS 工艺中 DEMOS 晶体管的闩锁
The dependence of device structures on latchup immunity in a 0.25-mum high-voltage (HV) 40-V CMOS process with drain-extended MOS (DEMOS) transistors has been verified with silicon test chips and investigated with device simulation. Layout parameters such as anode-to-cathode spacing and guard ring width are also investigated to find their impacts on latchup immunity. It was demonstrated that the drain-extended NMOS with a specific isolated device structure can greatly enhance the latchup immunity. The proposed test structures and simulation methodologies can be applied to extract safe and compact design rule for latchup prevention of DEMOS transistors in HV CMOS process