Low-VDD Operation of SRAM Synaptic Array for Implementing Ternary Neural Network
Low-VDD Operation of SRAM Synaptic Array for Implementing Ternary Neural Network
复制标题
用于实现三元神经网络的 SRAM 突触阵列的低 VDD 操作
DOI：
10.1109/tvlsi.2017.2727528
复制
发表时间：
2017
影响因子：
2.8
通讯作者：
Shimeng Yu
中科院分区：
文献类型：
--
作者：
Xiaoyu Sun;Rui Liu;Yi;Hsiao;Wei;Meng;Shimeng Yu
对于物联网（IoT）边缘设备，具有本地灵敏度能力，而不是将所有数据发送回云以进行图像模式识别。为了有效地实现IoT Edge设备的片上学习算法，已经提出了芯片合成记忆体系结构来实现关键操作，例如加权-SUM或矩阵矢量乘法。可以积极地降低到SRAM单元易于位的sraM芯片的测试结果。 1-0.55 V（或0.5 V）的位错误率〜0.23％（或〜1.56％），该分类精度仅引入〜0.08％（或〜1.68％）的降解。减少<inline-formula> <tex-math notege =“ latex”> $ 8 \ times $ </tex-math> </inline-formula>（或<inline-formula> <tex-math notegement ='乳胶“> $ 10 \ times $ </tex-math> </inline-formula>）。
For Internet of Things (IoT) edge devices, it is very attractive to have the local sensemaking capability instead of sending all the data back to the cloud for information processing. For image pattern recognition, neuro-inspired machine learning algorithms have demonstrated enormous powerfulness. To effectively implement learning algorithms on-chip for IoT edge devices, on-chip synaptic memory architectures have been proposed to implement the key operations such as weighted-sum or matrix-vector multiplication. In this paper, we proposed a low-power design of static random access memory (SRAM) synaptic array for implementing a low-precision ternary neural network. We experimentally demonstrated that the supply voltage (VDD) of the SRAM array could be aggressively reduced to a level, where the SRAM cell is susceptible to bit failures. The testing results from 65-nm SRAM chips indicate that VDD could be reduced from the nominal 1–0.55 V (or 0.5 V) with a bit error rate ~0.23% (or ~1.56%), which only introduced ~0.08% (or ~1.68%) degradation in the classification accuracy. As a result, the power consumption could be reduced by more than <inline-formula> <tex-math notation="LaTeX">$8\times $ </tex-math></inline-formula> (or <inline-formula> <tex-math notation="LaTeX">$10\times $ </tex-math></inline-formula>).