Floating-Point DSP Block Architecture for FPGAs
Floating-Point DSP Block Architecture for FPGAs
复制标题
适用于 FPGA 的浮点 DSP 模块架构
DOI：
--
复制
发表时间：
2015
期刊：
影响因子：
--
通讯作者：
B. Pasca
中科院分区：
文献类型：
--
作者：
M. Langhammer;B. Pasca
本文描述了一种支持固定和浮点运算的新型FPGA DSP块的结构。每个DSP模块可以配置为提供一个单精度IEEE-754浮点乘法器和一个IEEE-754浮点加法器，或者当配置为定点模式时，该模块完全向后兼容当前的FPGA DSP模块。两种模式下的DSP块工作频率相似，在500MHz范围内，每个块提供高达2 gmac的固定点和1 GFLOPs的性能。在浮点模式下，提供了对多块矢量模式的支持，其中多个块可以无缝地组装成任何大小的实数或复数点积。通过对定点算法模块和定点路由的有效重用，使浮点特性对功耗和面积的影响最小。我们展示了如何在现代Arria 10 FPGA家族中实现这些块，仅使用嵌入式结构提供超过1 TFLOPs，以及如何在规划的设备中扩展到多个TFLOPs密度。
This work describes the architecture of a new FPGA DSP block supporting both fixed and floating point arithmetic. Each DSP block can be configured to provide one single precision IEEE-754 floating multiplier and one IEEE-754 floating point adder, or when configured in fixed point mode, the block is completely backwards compatible with current FPGA DSP blocks. The DSP block operating frequency is similar in both modes, in the region of 500MHz, offering up to 2 GMACs fixed point and 1 GFLOPs performance per block. In floating point mode, support for multi-block vector modes are provided, where multiple blocks can be seamlessly assembled into any size real or complex dot products. By efficient reuse of the fixed point arithmetic modules, as well as the fixed point routing, the floating point features have only minimal power and area impact. We show how these blocks are implemented in a modern Arria 10 FPGA family, offering over 1 TFLOPs using only embedded structures, and how scaling to multiple TFLOPs densities is possible for planned devices.