Pattern independent maximum current estimation in power and ground buses of CMOS VLSI circuits: Algorithms, signal correlations, and their resolution
Pattern independent maximum current estimation in power and ground buses of CMOS VLSI circuits: Algorithms, signal correlations, and their resolution
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CMOS VLSI 电路的电源和接地总线中与模式无关的最大电流估计：算法、信号相关性及其分辨率
DOI：
10.1109/43.402499
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发表时间：
1995
期刊：
影响因子：
--
通讯作者：
I. Hajj
中科院分区：
文献类型：
--
作者：
H. Kriplani;F. Najm;I. Hajj
在CMOS数字电路的电源和接地（P&G）总线中流动的电流通过引起过大的电压降而影响电路的可靠性和性能。过大的电压降表现为P&G总线上的毛刺，并导致错误的逻辑信号和开关速度下降。最大电流估计需要在每个接触点的总线，以研究电压降问题的严重性，并重新设计相应的供电线路。然而，这些电流取决于应用于电路的特定输入模式。由于枚举所有可能的输入模式的成本高得令人望而却步，这个问题在很长一段时间内基本上没有得到解决。在本文中，我们提出了一种模式独立的，线性时间算法（iMax），估计在每个接触点，上限包络的所有可能的电流波形，结果通过应用不同的输入模式的电路。该算法是非常有效的，并产生良好的效果，为大多数电路的几个基准电路的实验结果证明。该算法的精度可以通过解决电路内部存在的信号相关性来进一步提高。我们还提出了一种新的部分输入枚举（PIE）技术，以解决信号的相关性，并显着提高了电路的上限，iMax产生的边界不紧。我们建立了广泛的实验结果，这些算法代表了一个很好的时间精度的权衡，并适用于超大规模集成电路。>
Currents flowing in the power and ground (P&G) buses of CMOS digital circuits affect both circuit reliability and performance by causing excessive voltage drops. Excessive voltage drops manifest themselves as glitches on the P&G buses and cause erroneous logic signals and degradation in switching speeds. Maximum current estimates are needed at every contact point in the buses to study the severity of the voltage drop problems and to redesign the supply lines accordingly. These currents, however, depend on the specific input patterns that are applied to the circuit. Since it is prohibitively expensive to enumerate all possible input patterns, this problem has, for a long time, remained largely unsolved. In this paper, we propose a pattern-independent, linear time algorithm (iMax) that estimates at every contact point, an upper bound envelope of all possible current waveforms that result by the application of different input patterns to the circuit. The algorithm is extremely efficient and produces good results for most circuits as is demonstrated by experimental results on several benchmark circuits. The accuracy of the algorithm can be further improved by resolving the signal correlations that exist inside a circuit. We also present a novel partial input enumeration (PIE) technique to resolve signal correlations and significantly improve the upper bounds for circuits where the bounds produced by iMax are not tight. We establish with extensive experimental results that these algorithms represent a good time-accuracy trade-off and are applicable to VLSI circuits. >