Performance and power analysis of time-multiplexed execution on dynamically reconfigurable processor
Performance and power analysis of time-multiplexed execution on dynamically reconfigurable processor
复制标题
动态可重构处理器上时分复用执行的性能和功耗分析
DOI:
10.1109/ipdps.2006.1639431
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发表时间:
2006
期刊:
影响因子:
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通讯作者:
H. Amano
中科院分区:
文献类型:
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作者:
Yohei Hasegawa;Shohei Abe;Shunsuke Kurotaki;Vu Manh Tuan;Naohiro Katsura;Takuro Nakamura;T. Nishimura;H. Amano
Dynamically reconfigurable processor (DRP) developed by NEC Electronics is a coarse grain reconfigurable processor that selects a datapath called a context from the on-chip repository of sixteen circuit configurations at runtime. The time-multiplexed execution based on the multi-context functionality is expected to drastically improve area and power efficiency. To demonstrate the impact of the time-multiplexed execution, we have implemented several stream applications on DRP with various context sizes. Throughout the evaluation based on real application designs, we analyzed the impact of the time-multiplexed execution on performance and power dissipation quantitatively.
DOI:
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发表时间:
2005
期刊:
Proceedings of IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS-2005)
影响因子:
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作者:
Matsunaga;R.;Abe;J.;Syunsuke Kurotaki
通讯作者:
Syunsuke Kurotaki