Circuit optimization using device layout motifs
Circuit optimization using device layout motifs
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DOI：
10.1109/vari.2014.6957081
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发表时间：
2014-11
期刊：
影响因子：
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通讯作者：
Yang Xiao;M. Trefzer;Scott Roy;James Alfred Walker;S. Bale;A. Tyrrell
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文献类型：
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作者：
Yang Xiao;M. Trefzer;Scott Roy;James Alfred Walker;S. Bale;A. Tyrrell
当技术达到原子尺度时，电路性能会受到晶体管内部电性能变化的显著影响，例如随机掺杂剂波动（RDF）、线边缘粗糙度（LER）和布局驱动变化。这增加了设计人员寻找更有效地减轻器件参数波动影响和提高电路性能的方法的压力。本文提出了一种新颖的器件布局样式：o形器件布局基序。为了研究和利用o形器件在器件级和电路级的变异性特性，采用TCAD仿真方法对包含LER变异性源的三维o形器件进行了仿真。从TCAD仿真结果中提取了相应的统计变异性模型，使SPICE能够有效地进行电路级仿真。为了进一步探讨这种新颖的器件布局母题对电路设计的影响，使用这种新型器件构建了一些逻辑门作为候选器件。实验结果表明，将o形器件与规则器件混合组合可以降低逻辑门的最差情况延迟。同时，变异性对传输延迟的影响可以得到缓解。
As technology reaches atomic scales, circuit performance is significantly affected by the variability of electrical properties within transistors such as random dopant fluctuation (RDF), line edge roughness (LER), and layout driven variations. This increases pressure on designers to find methodologies that more effectively mitigate the impact of device parameter fluctuations and improve circuit performance. In this paper, a novel alternative layout style of devices is proposed: an O-shaped device layout motif. A 3D O-shaped device simulation including LER variability source is performed using TCAD simulation in order to investigate and exploit the variability characteristics of O-shaped devices at both device level and circuit level. The corresponding statistical variability models enabling efficient circuit-level simulations using SPICE are extracted from TCAD simulation results. In order to further explore this novel device layout motif's impact on circuit design, a number of logic gates are used as candidates which are constructed using this novel device. The experimental results show that the worse case delay of logic gates can be reduced through mixed combinations of O-shaped devices and regular devices. At the same time, effects of variability on propagation delay can be mitigated.