Digital signal waveform improvement on VLSI packaging including inductances

Digital signal waveform improvement on VLSI packaging including inductances
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VLSI 封装上的数字信号波形改进(包括电感)

DOI:
10.1007/s10015-011-0915-y
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发表时间:
2011
期刊:
Artificial Life and Robotics (Springer)
影响因子:
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通讯作者:
and Moritoshi Yasunaga
and Moritoshi Yasunaga
中科院分区:
--
文献类型:
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作者:
Hiroki Shimada;Shohei Akita;Masami Ishiguro;Noriyuki Aibe;Ikuo Yoshihara;and Moritoshi Yasunaga

文献摘要

相似文献

随着印刷电路板(PCB)中数字信号频率的增加,波形失真或信号完整性(SI)问题变得越来越严重。SI问题变得严重的原因是需要将导线或迹线视为对电噪声敏感的传输线。为了克服这个问题,我们提出了一种新的方法,称为分段传输线(STL),并已显示其有效性,使用计算机模拟和基本原型。然而,在STL设计中,出现了组合爆炸问题。为了解决这个问题,遗传算法(GA)被用来设计STL。在这篇文章中,我们应用STL总线系统,包括电感,这来自超大规模集成电路(VLSI)封装。我们在模拟实验以及使用原型的实际实验中对STL进行了评估,并在实际实验中获得了1.53的最大改善率。
As the digital signal frequency in printed circuit boards (PCBs) increases, waveform distortion, or the signal integrity (SI) problem, is getting more and more serious. The reason the SI problem is becoming serious is that wires or traces need to be regarded as transmission lines which are sensitive to electric noise. In order to overcome this problem, we have proposed a novel methodology called a segmental transmission line (STL), and have shown its effectiveness using computer simulations and fundamental prototypes. However, in the STL design, the combinatorial explosion problem occurs. To solve this problem, a genetic algorithm (GA) was used to design the STL. In this article, we apply the STL to a bus system that includes inductances, which come from the very-large-scale integration (VLSI) packaging. We evaluated the STL in simulation experiments as well as actual experiments using prototypes, and obtained a maximum improvement ratio of 1.53 in the actual experiment.