Simultaneous Power and Thermal Integrity Driven Via Stapling in 3D ICs
Simultaneous Power and Thermal Integrity Driven Via Stapling in 3D ICs
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DOI：
10.1145/1233501.1233666
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发表时间：
2006-11
期刊：
影响因子：
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通讯作者：
Hao Yu;J. Ho;Lei He
中科院分区：
文献类型：
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作者：
Hao Yu;J. Ho;Lei He
现有的工作在3D集成电路中的过孔装订分别优化功率和热完整性，并使用稳态热分析。本文提出了第一个深入的研究，同时功率和热完整性驱动的过孔装订在3D设计。瞬态温度和电源电压违规计算的结构化和参数化的模型简化，这也产生参数化的温度和电压违规灵敏度相对于过孔图案和密度。利用参数化的灵敏度，提出了一种高效而有效的贪婪优化，以同时优化功率和热完整性。两个有源器件层的实验表明，相比于使用稳态热分析的顺序功率和热优化，使用瞬态热分析的顺序优化平均减少了11.5%的非信号通孔，使用瞬态热分析的同时优化平均减少了34%的非信号通孔。对于具有更多器件层的3D设计，通孔减少将更高
The existing work on via-stapling in 3D integrated circuits optimizes power and thermal integrity separately and uses steady-state thermal analysis. This paper presents the first in-depth study on simultaneous power and thermal integrity driven via-stapling in 3D design. The transient temperature and supply voltage violations are calculated by a structured and parameterized model reduction, which also generates parameterized temperature and voltage violation sensitivities with respect to the via pattern and density. Using parameterized sensitivities, an efficient yet effective greedy optimization is presented to optimize power and thermal integrity simultaneously. Experiments with two active device layers show that compared to sequential power and thermal optimization using steady-state thermal analysis, sequential optimization using transient thermal analysis reduces non-signal vias by on average 11.5%, and simultaneous optimization using transient thermal analysis reduces non-signal vias by on average 34%. The via reduction would be higher for the 3D design with more device layers