Benchmarking of Standard-Cell Based Memories in the Sub-$V_{ m T}$ Domain in 65-nm CMOS Technology
Benchmarking of Standard-Cell Based Memories in the Sub-$V_{
m T}$ Domain in 65-nm CMOS Technology
复制标题
65 nm CMOS 技术中 Sub-$V_{ m T}$ 域中基于标准单元的存储器的基准测试
DOI：
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发表时间：
2011
影响因子：
4.6
通讯作者：
J. Rodrigues
中科院分区：
文献类型：
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作者：
P. Meinerzhagen;Sherazi Yasser;A. Burg;J. Rodrigues
在本文中，标准单元为基础的存储器（SCM）提出了一种替代全定制子VT SRAM宏的超低功耗系统，需要小的内存块。每存储器访问的能量以及各种SCM架构的子VT域中可实现的最大吞吐量通过门级子VT表征模型进行评估，建立在从完全放置，路由和回注释网表中提取的数据上。在能量最小电压的各种SCM架构在65 nm CMOS技术考虑内管芯工艺参数的变化的可靠操作证明了通过蒙特卡罗电路模拟。最后，能量每存储器访问，可实现的吞吐量，和最好的SCM架构的面积相比，最近的子VT SRAM设计。
In this paper, standard-cell based memories (SCMs) are proposed as an alternative to full-custom sub-VT SRAM macros for ultra-low-power systems requiring small memory blocks. The energy per memory access as well as the maximum achievable throughput in the sub-VT domain of various SCM architectures are evaluated by means of a gate-level sub-VT characterization model, building on data extracted from fully placed, routed, and back-annotated netlists. The reliable operation at the energy-minimum voltage of the various SCM architectures in a 65-nm CMOS technology considering within-die process parameter variations is demonstrated by means of Monte Carlo circuit simulation. Finally, the energy per memory access, the achievable throughput, and the area of the best SCM architecture are compared to recent sub-VT SRAM designs.