DP-FPGA: An FPGA Architecture Optimized for Datapaths
DP-FPGA: An FPGA Architecture Optimized for Datapaths
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DOI：
10.1155/1996/95942
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发表时间：
1996
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影响因子：
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通讯作者：
D. Cherepacha;D. Lewis
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文献类型：
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作者：
D. Cherepacha;D. Lewis
本文提出了一种新的现场可编程门阵列（FPGA）结构，它减少了面向数据通路电路的FPGA和掩模编程门阵列（MPGA）之间的密度差距。这主要是通过将数据作为多个相同编程的四位片来操作来实现的。互连网络结合了用于路由控制和数据信号的不同资源集。这些功能通过在四位片之间共享编程位来减少电路面积，从而减少所需存储单元的总数。
This paper presents a new Field-Programmable Gate Array (FPGA) architecture which reduces the density gap between FPGAs and Mask-Programmed Gate Arrays (MPGAs) for datapath oriented circuits. This is primarily achieved by operating on data as a number of identically programmed four-bit slices. The interconnection network incorporates distinct sets of resources for routing control and data signals. These features reduce circuit area by sharing programming bits among four-bit slices, reducing the total number of storage cells required.