A 4-to-16GHz inverter-based injection-locked quadrature clock generator with phase interpolators for multi-standard I/Os in 7nm FinFET
A 4-to-16GHz inverter-based injection-locked quadrature clock generator with phase interpolators for multi-standard I/Os in 7nm FinFET
复制标题
基于 4 至 16GHz 逆变器的注入锁定正交时钟发生器，具有相位插值器，适用于 7nm FinFET 中的多标准 I/O
DOI：
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发表时间：
2018
期刊：
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通讯作者：
Ken Chang
中科院分区：
文献类型：
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作者：
S. Chen;Lei Zhou;Ian Zhuang;J. Im;Didem Turkur Melek;Jinyung Namkoong;M. Raj;Jaewook Shin;Y. Frans;Ken Chang
随着不断增长的带宽需求推动有线收发器数据速率超过25 Gb/s，在宽数据速率范围内支持多协议的时钟解决方案成为关键的设计挑战。在[1]中，一个注入锁定多相位时钟发生器演示了宽带操作和高分辨率相位旋转器使用CML在28 nm FDSOI CMOS。然而，在7 nm FinFET技术中，CML实施遭受降低的电源电平和高温下的输出阻抗退化。为了根据数据速率调整功耗，CML实现还需要采用偏置电流和负载可编程性，从而进一步影响其性能。基于这些原因，提出了基于电源调节逆变器的时钟方案。此外，基于全反相器的时钟链生成的随机抖动（RJ）更小，因为与CML实现相比，边沿速率更快。作为校准环路的一部分应用的电源调节可降低工艺和温度变化对逆变器延迟和边沿速率的敏感性。该设计采用了“栅海”布局方式，优化了通孔图案，并采用了均匀的金属走线，有效地降低了7 nm FinFET多层图形化工艺中底层金属寄生电阻的显著变化。
As ever-increasing bandwidth demand pushes wireline transceiver data-rates beyond 25Gb/s, the clocking solution for multi-protocol support over a wide range of data-rates becomes a key design challenge. In [1], an injection-locked multi-phase clock generator demonstrated wideband operation and a high-resolution phase rotator using CML in 28nm FDSOI CMOS. However, in 7nm FinFET technology, the CML implementation suffers from the reduced supply level and output impedance degradation at high temperatures. In order to scale power consumption with data-rate, CML implementation also needs to employ bias current and load programmability, further impacting its performance. For these reasons, the supply-regulated inverter-based clocking scheme is proposed. Furthermore, the full inverter-based clock chain generates smaller random jitter (RJ) because of the faster edge-rate compared to a CML implementation. Supply regulation, applied as part of the calibration loop, mitigates the sensitivity to inverter delay and edge-rate over the process and temperature variations. This design, benefiting from its mostly-digital structure, adopts “sea of gates” layout style with optimized via patterns and uniform metal tracks, which effectively alleviate the significant parasitic resistance variations on low level metals fabricated by multiple patterning in 7nm FinFET.