Design of a DSL for Converting Rust Programming Language into RTL
Design of a DSL for Converting Rust Programming Language into RTL
复制标题
将 Rust 编程语言转换为 RTL 的 DSL 设计
DOI：
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发表时间：
2020
期刊：
影响因子：
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通讯作者：
M. Kohata
中科院分区：
文献类型：
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作者：
Keisuke Takano;Tetsuya Oda;M. Kohata
最近的研究集中在流处理、大数据、深度学习等海量处理上。由于这些处理的处理时间与计算量成比例地增加，因此需要能够提高速度的算术单元。在这种情况下，现场可编程门阵列(现场可编程门阵列)因其能够加快处理速度、降低功耗而备受关注。然而，在开发现场可编程门阵列时，使用Verilog等硬件描述语言，增加了开发时间，也使得存储安全难以保证。本文提出了一种设计领域专用语言(DSL)的寄存器传输级(RTL)，用于Rust程序设计语言到RTL的转换。
Recent research has focused on a large amount of processing such as streaming processing, big data, deep learning and so on. Since the processing time of these processes increases in proportion to the amount of calculation, an arithmetic unit that can increase the speed is required. In this situation, Field Programmable Gate Array (FPGA) has been attracting attention because it can speed up processing and reduce power consumption. However, Hardware Description Language (HDL) such as Verilog used when developing FPGA increases the development time, but also makes it difficult to guarantee memory safety. In this paper, we propose a Register Transfer Level (RTL) designing Domain Specific Language (DSL) for Rust programming language convert to RTL.
影响因子：
16.6
作者：
Ivie, Peter;Thain, Douglas
通讯作者：
Thain, Douglas