ADRES & DRESC: Architecture and Compiler for Coarse-GrainReconfigurable Processors

ADRES & DRESC: Architecture and Compiler for Coarse-GrainReconfigurable Processors
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安德烈斯

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发表时间：
2007
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通讯作者：
J. Mignolet
J. Mignolet
中科院分区：
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文献类型：
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作者：
B. Mei;Mladen Berekovic;J. Mignolet

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如今，典型的嵌入式系统需要高性能才能执行在运行时进行视频编码/解码等任务。使用轻量级电池，它应该消耗几小时甚至几天的时间。它应该足够灵活，可以在一个单个设备中集成多个应用程序和标准。粗粒子可重新配置的体系结构（CGRA）正在成为应对上述挑战的潜在候选者。近年来提出了其中的许多。但是，现有的CGRA尚未广泛采用，这主要是由于对这种复杂体系结构的编程难度
Nowadays, a typical embedded system requires high performance to perform tasks such as video encoding/decoding at run-time. It should consume little energy to work hours or even days using a lightweight battery. It should be flexible enough to integrate multiple applications and standards in one single device. Coarse-grained reconfigurable architectures (CGRAs) are emerging as potential candidates to meet the above challenges. Many of them were proposed in recent years. However, existing CGRAs have yet been widely adopted mainly because of programming difficulty for such complex architecture