Fine-grained characterization of process variation in FPGAs
Fine-grained characterization of process variation in FPGAs
复制标题
FPGA 中工艺变化的细粒度表征
DOI：
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发表时间：
2010
期刊：
影响因子：
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通讯作者：
P. Leong
中科院分区：
文献类型：
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作者：
Haile Yu;Qiang Xu;P. Leong
随着半导体制造继续朝着减小特征尺寸的方向发展，由于工艺变化而导致的产量损失变得越来越重要。为了在FPGA平台上解决这个问题，已经提出了几种变化感知设计（VAD）方法。在这项工作中，我们提出了一个实用的方法，工艺变化特性（PVC），以促进VAD只使用固有的FPGA资源。该方案是基于测量之间的差异环形振荡器（RO）延迟在不同的位置在一个管芯，并可以用来执行LE延迟和互连延迟，包括直接连接，双线和六角线的工艺变化特性。环路延迟的差异也可以使用从基元提取的参数从方程中估计，并与直接测量进行比较。在Xilinx Spartan-3e设备上，发现估计值和测量值之间的误差平均小于10%。
As semiconductor manufacturing continues towards reduced feature sizes, yield loss due to process variation becomes increasingly important. To address this issue on FPGA platforms, several variation aware design (VAD) methodologies have been proposed. In this work we present a practical method of process variation characterization (PVC) to facilitate VAD using only intrinsic FPGA resources. The scheme is based on measuring the difference between ring oscillator (RO) delay at different locations within a die, and can be used to perform process variation characterization for LE delays and interconnect delays including direct connection, double wire and hex wires. The difference in loop delays can also be estimated from equations using parameters extracted from primitives and compared with direct measurements. On a Xilinx Spartan-3e device, it was found that the error between the estimated and measured values was on average less than 10%.