Virtual-physical registers
Virtual-physical registers
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虚拟-物理寄存器
DOI：
10.1109/hpca.1998.650557
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发表时间：
1998
期刊：
影响因子：
--
通讯作者：
M. Valero
中科院分区：
文献类型：
--
作者：
Antonio González;José González;M. Valero
提出了一种新的动态寄存器重命名方法。新方案的关键思想是延迟物理寄存器的分配，直到流水线的后期阶段，而不是像传统方案那样在解码阶段进行。通过这种方式，寄存器压力得以降低，并且处理器可以利用更多的并行级并行性。延迟物理寄存器的分配需要一些额外的工件来跟踪依赖性。这是通过引入虚拟物理寄存器的概念来实现的，虚拟物理寄存器不需要任何存储位置，并且用于识别尚未将寄存器分配给其目的地操作数的指令之间的依赖性。已经研究了两种替代的分配策略，它们在物理寄存器分配的阶段不同：发布或回写。实验评价证实了后一种替代方案的更高性能。我们已经通过一个详细的模拟动态调度处理器的新方案进行了所有的评估。结果显示出显著的改善（例如，与传统的寄存器重命名方法相比，每个文件中有64个物理寄存器的机器的IPC增加了19%。
A novel dynamic register renaming approach is proposed in this work. The key idea of the novel scheme is to delay the allocation of physical registers until a late stage in the pipeline, instead of doing it in the decode stage as conventional schemes do. In this way, the register pressure is reduced and the processor can exploit more instruction-level parallelism. Delaying the allocation of physical registers require some additional artifact to keep track of dependences. This is achieved by introducing the concept of virtual-physical registers, which do not require any storage location and are used to identify dependences among instructions that have not yet allocated a register to its destination operand. Two alternative allocation strategies have been investigated that differ in the stage where physical registers are allocated: issue or write-back. The experimental evaluation has confirmed the higher performance of the latter alternative. We have performed all evaluation of the novel scheme through a detailed simulation of a dynamically scheduled processor. The results show a significant improvement (e.g., 19% increase in IPC for a machine with 64 physical registers in each file) when compared with the traditional register renaming approach.