Spur-Free Multirate All-Digital PLL for Mobile Phones in 65 nm CMOS
Spur-Free Multirate All-Digital PLL for Mobile Phones in 65 nm CMOS
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DOI：
10.1109/jssc.2011.2162769
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发表时间：
2011-08
影响因子：
5.4
通讯作者：
R. Staszewski;K. Waheed;F. Dulger;O. Eliezer
中科院分区：
文献类型：
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作者：
R. Staszewski;K. Waheed;F. Dulger;O. Eliezer
我们提出了一种新的多速率架构的全数字锁相环（ADPLL）具有相位/频率调制能力。虽然ADPLL方法已经通过离散时间操作和纳米级CMOS中的完全RF SoC集成证明了其功耗和成本降低的优势，但鉴相器功能的粗略离散化往往使其无法达到RF性能潜力的极限。建议的ADPLL具有任意高的数据速率调制，是独立于参考频率。还通过具有差分对失配的动态调整的抖动以及反馈时钟的频率转换，使得其基本上没有TDC的注入牵引和病态量化噪声。采用了推测时钟重定时和异步计数器等低功耗技术。该ADPLL采用65 nm CMOS实现，作为单芯片GSM/EDGE RF-SoC的一部分。它占地0.35 mm 2，在低频带1.2 V电源下消耗32 mA电流。测量结果表明，一个几乎无毛刺的操作。
We propose a new multirate architecture of an all-digital PLL (ADPLL) featuring phase/frequency modulation capability. While the ADPLL approach has already proven its benefits of power dissipation and cost reduction through the discrete-time operation and full RF-SoC integration in nanoscale CMOS, the coarse discretization of the phase detector function tends to keep it from reaching the ultimate of the RF performance potential. The proposed ADPLL features an arbitrarily high data rate modulation that is independent from the reference frequency. It is also made substantially free from injection pulling and ill-shaped quantization noise of the TDC by means of dithering with dynamic adjustment of differential pair mismatches as well as frequency translation of the feedback clock. Low power techniques, such as speculative clock retiming and asynchronous counter are used. The presented ADPLL is implemented in 65 nm CMOS as part of a single-chip GSM/EDGE RF-SoC. It occupies 0.35 mm2 and consumes 32 mA of current at 1.2 V supply in the low frequency band. The measured results show a virtually spur-free operation.