A Scalable Decoder Architecture for IEEE 802.11n LDPC Codes
A Scalable Decoder Architecture for IEEE 802.11n LDPC Codes
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IEEE 802.11n LDPC 码的可扩展解码器架构
DOI：
10.1109/glocom.2007.620
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发表时间：
2007
期刊：
影响因子：
--
通讯作者：
L. Fanucci
中科院分区：
文献类型：
--
作者：
M. Rovini;Giuseppe Gentile;F. Rossi;L. Fanucci
本文描述了符合 IEEE 802.1 In 并运行众所周知的分层解码算法的 LDPC 码解码器的可扩展 IP。解码器架构以串行处理单元集群的形式排列，这些单元可配置为处理标准中的所有代码，同时支持多帧解码。还描述了迭代延迟的优化方法，该方法与处理器更新消息的顺序以及解码器经过的层的顺序有关。采用低功耗标准单元库的 65 nm CMOS 技术的逻辑综合表明，所提出的设计适用于便携式设备，吞吐量范围为 180 至 410 Mbps，功耗低于 235 mW。
This paper describes a scalable IP of a decoder for LDPC codes compliant to IEEE 802.1 In and running the well- known layered decoding algorithm. The decoder architecture is arranged in clusters of serial processing units, which are configurable to process all the codes in the standard and, at the same time, to support multiple frame decoding. An optimization methodology of the iteration latency is also described, which relates to the order of the messages updated by the processors, as well as to the sequence of layers the decoder goes through. The logic synthesis on 65 nm CMOS technology with low- power standard-cell library, shows that the proposed design is suitable for portable devices, the throughput ranging from 180 to 410 Mbps, and the power consumption being below 235 mW.