FPGA based implementation of baseline JPEG decoder
FPGA based implementation of baseline JPEG decoder
复制标题
基于 FPGA 的基线 JPEG 解码器实现
DOI：
10.1145/1838002.1838035
复制
发表时间：
2009
影响因子：
12.3
通讯作者：
S. M. U. Talha
中科院分区：
文献类型：
--
作者：
Jahanzeb Ahmad;Kamran Raza;Mansoor Ebrahim;S. M. U. Talha
JPEG标准（ISO/IEC 10918-1 ITU-T Recommendation T.81）定义了用于图像数据的压缩技术。因此，它允许存储和传输图像数据，大大降低了对存储空间和带宽的需求。从JPEG标准中提供的四种进程中，只有一种，即基线进程被广泛使用。本文提出了一种基于FPGA的JPEG解码器的高速、低复杂度、低内存实现方案。该系统的流水线实现，允许同时解压缩多个图像块。硬件解码器设计为在Altera Cyclon II或Xilinx Spartan 3E FPGA或等效器件上以100 MHz运行。该解码器能够解码基线JPEG彩色和灰度图像。解码器还能够将图像缩小8。解码器的设计是为了满足工业需求。设计中实现了JFIF、DCF和EXIF标准
The JPEG standard (ISO/IEC 10918-1 ITU-T Recommendation T.81) defines compression techniques for image data. As a consequence, it allows to store and transfer image data with considerably reduced demand for storage space and bandwidth. From the four processes provided in the JPEG standard, only one, the baseline process is widely used. In this paper FPGA based High speed, low complexity and low memory implementation of JPEG decoder is presented. The pipeline implementation of the system, allow decompressing multiple image blocks simultaneously. The hardware decoder is designed to operate at 100MHz on Altera Cyclon II or Xilinx Spartan 3E FPGA or equivalent. The decoder is capable of decoding Baseline JPEG color and gray images. Decoder is also capable of downscaling the image by 8. The decoder is designed to meet industrial needs. JFIF, DCF and EXIF standers are implemented in the design