Efficient Compression-Based Line Buffer Design for Image/Video Processing Circuits
Efficient Compression-Based Line Buffer Design for Image/Video Processing Circuits
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DOI：
10.1109/tvlsi.2019.2921249
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发表时间：
2019-10
影响因子：
2.8
通讯作者：
Hang Wang;Tiancheng Wang;Longjun Liu;Hongbin Sun;Nanning Zheng
中科院分区：
文献类型：
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作者：
Hang Wang;Tiancheng Wang;Longjun Liu;Hongbin Sun;Nanning Zheng
行缓冲器是用于图像/视频处理电路的一种典型且主要的片上存储器设计结构。由于它通常占用很大的片上电路面积，因此通过有效的体系结构设计来降低其硬件成本具有重要意义。数据压缩是提高行缓冲结构硬件效率的一种很有前途的技术。然而，以前提出的针对行缓冲结构的数据压缩技术仅采用定长编码(FLC)，这实际上在压缩性能上存在不足。相反，本文探讨了如何在行缓冲结构中有效地使用变长码。通过将可变长度编码限制在较小的压缩粒度(CG)内，该压缩算法不仅显著提高了压缩性能，而且满足了行缓冲体系结构设计的特定要求。简单的压缩算法进一步实现了高效和全流水线的VLSI架构和电路。实验结果表明，与FLC设计相比，该压缩算法在压缩比为50%、CG为16像素的情况下，峰值信噪比提高了6.67-d B。在合理的硬件成本下，采用该压缩方案的VLSI电路在60fps时的吞吐量可以达到4K$\Text{K}$。在行缓冲结构中使用所提出的压缩技术可以在保持满意的视觉质量的同时显著降低片上存储成本。
Line buffer is a typical and major on-chip memory design architecture for image/video processing circuits. As it usually occupies very large on-chip circuit area, it is of great importance to reduce its hardware cost through efficient architecture design. Data compression is a promising technique to improve the hardware efficiency of line buffer architecture. Nevertheless, the previously proposed data compression technique for line buffer architecture only exploits fixed length code (FLC), which actually has the deficiency on compression performance. Instead, this paper explores to efficiently use variable length code in line buffer architecture. By restricting variable length coding within small compression granularity (CG), the proposed compression algorithm not only significantly improves compression performance but also meets the specific requirements in line buffer architecture design. The simple compression algorithm further enables the efficient and fully pipelined VLSI architecture and circuits. Experimental results demonstrate that the proposed compression algorithm achieves 6.67-dB peak signal-to-noise ratio improvement at the compression ratio of 50% and the CG of 16 pixels, compared with FLC design. The VLSI circuits of the proposed compression can achieve the throughput of 4K $\times2\text{K}$ at 60 fps with reasonable hardware cost. The use of the proposed compression technique in line buffer architecture can significantly reduce on-chip memory cost while maintaining satisfactory visual quality.