Countering Load-to-Use Stalls in the NVIDIA Turing GPU
Countering Load-to-Use Stalls in the NVIDIA Turing GPU
复制标题
解决 NVIDIA Turing GPU 中的加载使用停顿问题
DOI:
10.1109/mm.2020.3012514
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发表时间:
2020
期刊:
影响因子:
3.6
通讯作者:
Alexandre Joly
中科院分区:
文献类型:
--
作者:
Ram Rangan;Naman Turakhia;Alexandre Joly
Among its various improvements over prior NVIDIA GPUs, the NVIDIA Turing GPU boasts of four key performance enhancements to effectively counter memory load-to-use stalls. First, reduced latency on L1 hits for global memory loads helps lower average memory lookup latency. Next, the ability to dynamically configure the L1 data RAM between cacheable memory and scratchpad or shared memory, enables driver software to opportunistically maximize L1 data cache size for programs with low shared memory requirements, increasing L1 hits and reducing load-to-use stalls. Finally, the twin enhancements of doubling of vector register file capacity and the addition of a dedicated scalar or uniform register file along with a uniform datapath, ease vector register pressure and enable higher warp level parallelism, leading to better latency tolerance. We find that the above enhancements combined deliver an average speedup of 11% on modern gaming applications.