Critical charge concepts for CMOS SRAMs
Critical charge concepts for CMOS SRAMs
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DOI:
10.1109/23.488777
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发表时间:
1995-12-01
影响因子:
1.8
通讯作者:
Sexton, FW
中科院分区:
文献类型:
--
作者:
Dodd, PE;Sexton, FW
The dramatic effects of external circuit loading on the heavy-ion-induced charge-collection response of a struck transistor are illustrated using three-dimensional mixed-mode simulations. Simulated charge-collection and SEU characteristics of a CMOS SRAM cell indicate that, in some cases, more charge can be collected at sensitive nodes from strikes that do not cause upset than from strikes that do cause upset. Computations of critical charge must take into account the time during which charge is collected, not simply the total amount of charge collected. Model predictions of the incident linear energy transfer required to cause upset agree well with measured data for CMOS SRAMs, without parameter adjustments. The results show the absolute necessity of treating circuit effects in any realistic device simulation of single-event upset (SEU) in SRAMs.