Efficient Cache Architecture for Table Lookups in an Internet Router
Efficient Cache Architecture for Table Lookups in an Internet Router
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DOI：
10.14569/ijacsa.2020.0110581
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发表时间：
2020
影响因子：
0.9
通讯作者：
Hayato Yamaki
中科院分区：
文献类型：
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作者：
Hayato Yamaki
从数据包处理吞吐量和功耗的角度来看，查找是路由器中最重要的操作。为了实现高吞吐量、低能耗的查表，提出了分组处理缓存（PPC）。PPC将表查找结果存储到每个流的小型SRAM（静态随机存取存储器）中，并重用缓存的结果来处理同一流的后续数据包。因为SRAM以比TCAM（三进制内容可寻址存储器）更快的速度和显著更低的能量被访问，TCAM（三进制内容可寻址存储器）传统上被用作用于在路由器中存储表的存储器，所以当分组的表查找结果在PPC中时，PPC可以以更高的吞吐量和更低的功耗来处理分组。尽管PPC性能取决于PPC命中/未命中率，但是最近的PPC仍然显示出高PPC未命中率并且不能实现足够的性能。在本文中，高效的缓存架构，构造两种不同的技术，提出了提高PPC的未命中率。仿真结果表明，与传统PPC架构相比，它们的组合方法实现了1.72倍的吞吐量，能耗降低了41.4%。
Table lookup is the most important operation in routers from the aspects of both packet processing throughput and power consumption. To realize the table lookup at high throughput with low energy, Packet Processing Cache (PPC) has been proposed. PPC stores table lookup results into a small SRAM (static random access memory) per flow and reuses the cached results to process subsequent packets of the same flow. Because the SRAM is accessed faster with significant lower energy than TCAM (Ternary Content Addressable Memory), which is conventionally used as a memory for storing the tables in routers, PPC can process packets at higher throughput with lower power consumption when the table lookup results of the packets are in PPC. Although the PPC performance depends on the PPC hit/miss rates, recent PPCs still show high PPC miss rates and cannot achieve sufficient performance. In this paper, efficient cache architecture, constructed of two different techniques, is proposed to improve the PPC miss rate more. The simulation results indicated that the combined approach of them achieved 1.72x larger throughput with 41.4% lower energy consumption in comparison to the conventional PPC architecture.