A compact quick-start sub-mW pulse-width-controlled PLL with automated layout synthesis using a place-and-route tool
A compact quick-start sub-mW pulse-width-controlled PLL with automated layout synthesis using a place-and-route tool
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DOI：
10.1587/elex.16.20190546
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发表时间：
2019
期刊：
影响因子：
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通讯作者：
Wang Jing;T. Iizuka;Zule Xu;T. Nakura
中科院分区：
文献类型：
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作者：
Wang Jing;T. Iizuka;Zule Xu;T. Nakura
本文演示了一种快速启动脉宽控制PLL的设计流程，该PLL使用布局布线工具进行自动布局综合。快速启动PWPLL将内部状态转换为模拟-数字混合信号，称为软温度计码（STC），并在PWPLL开启前将其存储到存储器中，以增强下一次开启时的启动能力，采用TSMC 65 nm工艺制作的芯片的建立时间为220 ns（13个参考时钟周期），1V标称电源电压下的功耗为858µW，硅面积为59µm × 58µm。测量结果表明，自动设计的PLL实现了-221.7dB的FoM，这与具有相同目标规格的手动设计的FoM大致相同。
This paper demonstrates the design fl ow of a quick-start pulse-width-controlled PLL with automated layout synthesis using a place-and- route tool. The quick-start PWPLL converts the internal state into an analog-digital mixed signal called soft-thermometer-code (STC) and stores them into memory before PWPLL is turned o ff in order to enhance the start-up in the next turn-on. Our chip fabricated with TSMC 65nm shows 220ns settling time (13 reference clock cycles), 858µW power consumption under 1V nominal supply voltage with 59µm × 58µm silicon area. The measurement results demonstrate that the design-automated PLL realizes the FoM of − 221.7dB, which is roughly the same value as that of the manually-designed one with the same target speci fi cation.