A 14-Gb/s 32 mW AC coupled receiver in 90-nm CMOS
A 14-Gb/s 32 mW AC coupled receiver in 90-nm CMOS
复制标题
采用 90 nm CMOS 的 14 Gb/s 32 mW 交流耦合接收器
DOI：
10.1109/vlsic.2007.4342754
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发表时间：
2007
期刊：
影响因子：
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通讯作者：
A. C. Carusone
中科院分区：
文献类型：
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作者：
M. Hossain;A. C. Carusone
本文介绍了一种用于高密度互连的高速交流耦合接收机结构。所提出的架构结合了一种新型的磁滞电路路径和线性宽带放大器路径，从80-fF的电容耦合通道恢复NRZ信号。使用这种双路径技术，一个90纳米CMOS原型实现14 Gb/s的操作，而消耗32 mW的1.2 V电源。接收机的测量灵敏度优于100 mVp-p差分。
This paper introduces a high-speed AC coupled receiver architecture for high density interconnects. The proposed architecture combines a novel hysteresis circuit path and a linear broadband amplifier path to recover a NRZ signal from an 80-fF capacitively coupled channel. Using this dual path technique, a 90-nm CMOS prototype achieves 14-Gb/s operation while consuming 32 mW from a 1.2-V supply. The measured sensitivity of the receiver is better than 100 mVp-p differential.