Performance-driven Wire Sizing for Analog Integrated Circuits
Performance-driven Wire Sizing for Analog Integrated Circuits
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DOI：
10.1145/3559542
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发表时间：
2022-08
影响因子：
1.4
通讯作者：
Yaguang Li;Yishuang Lin;Meghna Madhusudan;A. Sharma;S. Sapatnekar;R. Harjani;Jiang Hu
中科院分区：
文献类型：
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作者：
Yaguang Li;Yishuang Lin;Meghna Madhusudan;A. Sharma;S. Sapatnekar;R. Harjani;Jiang Hu
模拟IC性能对互连RC寄生效应有很强的依赖性，在最新技术中，互连RC寄生效应受导线尺寸的影响很大，其中最小宽度导线具有高电阻。然而，模拟IC的性能驱动的布线尺寸很少受到研究关注。为了填补这一空白，我们开发了几种技术，以促进端到端的自动电线尺寸的方法。它们包括基于自定义图神经网络（GNN）的电路性能模型和两种优化技术：一种使用由GNN模型加速的贝叶斯优化，另一种基于TensorFlow训练。实验结果表明，我们的技术可以实现11%的电路性能提高或8.7倍的加速比相比，传统的贝叶斯优化方法。
Analog IC performance has a strong dependence on interconnect RC parasitics, which are significantly affected by wire sizes in recent technologies, where minimum-width wires have high resistance. However, performance-driven wire sizing for analog ICs has received very little research attention. In order to fill this void, we develop several techniques to facilitate an end-to-end automatic wire sizing approach. They include a circuit performance model based on customized graph neural network (GNN) and two optimization techniques: one using Bayesian optimization accelerated by the GNN model, and the other based on TensorFlow training. Experimental results show that our technique can achieve 11% circuit performance improvement or 8.7× speedup compared to a conventional Bayesian optimization method.