Trip-Point Bit-Line Precharge Sensing Scheme for Single-Ended SRAM
Trip-Point Bit-Line Precharge Sensing Scheme for Single-Ended SRAM
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DOI：
10.1109/tvlsi.2014.2337958
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发表时间：
2015-07
影响因子：
2.8
通讯作者：
Hanwool Jeong;Taewon Kim;T. Song;Gyu-Hong Kim;Seong-ook Jung
中科院分区：
文献类型：
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作者：
Hanwool Jeong;Taewon Kim;T. Song;Gyu-Hong Kim;Seong-ook Jung
提出了一种适用于高速单端静态随机存取存储器(SRAM)的跳跃点位线预充电(TBP)检测方案。这种TBP方案通过将位线偏置到略大于读出放大器的跳变点的值，缓解了在以前的单端SRAM读出方案中发现的有限的性能、功率、读出裕度和面积的问题。仿真结果表明，TBP感知方案与多米诺骨牌和交流耦合感知方案相比，感知时间分别减少了58.5%和10%。此外，与交流耦合传感方案相比，该方案的传感功率降低了10%，面积减少了36%，目标传感产量的最小电源电压降低了60 mV。
A trip-point bit-line precharge (TBP) sensing scheme is proposed for high-speed single-ended static random-access memory (SRAM). This TBP scheme mitigates the issues of limited performance, power, sensing margin, and area found in the previous single-ended SRAM sensing schemes by biasing the bit-line to a slightly larger value than the trip point of the sense amplifier. Simulation results show that the TBP sensing scheme can reduce the sensing time by 58.5% and 10% compared with the domino and ac-coupled sensing schemes, respectively. Further, compared with the ac-coupled sensing scheme, the proposed scheme offers 10% lower sensing power, 36% lesser area, and a 60 mV lower value of the minimum supply voltage for the target sensing yield.