Cell transformations and physical design techniques for 3D monolithic integrated circuits
Cell transformations and physical design techniques for 3D monolithic integrated circuits
复制标题
3D单片集成电路的单元变换和物理设计技术
DOI：
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发表时间：
2013
期刊：
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通讯作者：
G. Micheli
中科院分区：
文献类型：
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作者：
Shashikanth Bobba;A. Chakraborty;O. Thomas;P. Batude;G. Micheli
3D单片集成（3DMI），也称为顺序集成，是未来千兆级电路的潜在技术。在 3DMI 技术中，连接不同有源层的 3D 接触尺寸约为 100nm。鉴于如此小的接触点的优势，3DMI 可以实现电路的细粒度（门级）分区。在这项工作中，我们提出了采用 3DMI 技术的三种基于标准单元 IC 的单元转换技术。作为这项工作的主要贡献，我们提出了一种设计流程，包括单元转换技术、单元间堆叠和物理设计技术 (CELONCELPD)，旨在放置通过单元间堆叠转换的单元。我们分析并比较了 3DMI 技术的各种单元转换技术，而不破坏 IC 设计流程的规律性。我们的实验证明了 CELONCEL 设计技术的有效性，在 45nm 技术节点的各种设计中进行基准测试时，与 2D 案例相比，面积减少了 37.5%，线长平均减少了 16.2%，总体延迟平均改善了 6.2%。
3D Monolithic Integration (3DMI), also termed as sequential integration, is a potential technology for future gigascale circuits. In 3DMI technology the 3D contacts, connecting different active layers, are in the order of few 100nm. Given the advantage of such small contacts, 3DMI enables fine-grain (gate-level) partitioning of circuits. In this work we present three cell transformation techniques for standard cell-based ICs with 3DMI technology. As a major contribution of this work, we propose a design flow comprising of a cell transformation technique, cell-on-cell stacking, and a physical design technique (CELONCELPD) aimed at placing cells transformed with cell-on-cell stacking. We analyze and compare various cell transformation techniques for 3DMI technology without disrupting the regularity of the IC design flow. Our experiments demonstrate the effectiveness of CELONCEL design technique, yielding us an area reduction of 37.5%, 16.2% average reduction in wirelength, and 6.2% average improvement in overall delay, compared with a 2D case when benchmarked across various designs in 45nm technology node.