All-Digital Circuit-Level Dynamic Variation Monitor for Silicon Debug and Adaptive Clock Control
All-Digital Circuit-Level Dynamic Variation Monitor for Silicon Debug and Adaptive Clock Control
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用于芯片调试和自适应时钟控制的全数字电路级动态变化监视器
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发表时间：
2011
期刊：
影响因子：
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通讯作者：
V. De
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作者：
K. Bowman;Carlos Tokunaga;J. Tschanz;A. Raychowdhury;M. Khellah;B. Geuskens;Shih;Paolo A. Aseron;T. Karnik;V. De
45 nm 微处理器集成了全数字动态变化监视器 (DVM)，可连续测量动态参数变化对电路级性能的影响，从而增强芯片调试和自适应时钟控制。 DVM 由可调复制电路、时间数字转换器和多路复用器组成，用于测量电路延迟或频率变化，测量分辨率误差小于 1%，同时捕获时钟与数据的相关性。在使用微处理器最大时钟频率 (FMAX) 测量来验证 DVM 时，片上噪声注入器电路会在测试程序中的特定周期引起电源电压 (VCC) 下降。然后，FMAX 测量会重复超过一千次迭代，同时每次迭代将下垂位置转移到不同的周期。硅测量证明了 DVM 能够在各种 VCC 压降曲线下跟踪最坏情况下 FMAX 降低至 1% 以内的情况。此外，硅测量表明，FMAX 对程序执行期间高频 VCC 下降的位置和幅度高度敏感，从而凸显了 DVM 对于硅调试的价值。此外，DVM与自适应时钟控制电路连接，通过改变锁相环中的分频比来动态调整时钟频率，以响应持续的变化，使微处理器能够适应操作环境以获得最大效率。
A 45 nm microprocessor integrates an all-digital dynamic variation monitor (DVM) to continuously measure the impact of dynamic parameter variations on circuit-level performance to enhance silicon debug and adaptive clock control. The DVM consists of a tunable replica circuit, a time-to-digital converter, and multiplexers to measure circuit delay or frequency changes with less than a 1% measured resolution error while capturing clock-to-data correlations. In validating the DVM with microprocessor maximum clock frequency (FMAX) measurements, an on-die noise injector circuit induces a supply voltage (VCC) droop at a particular cycle in the test program. The FMAX measurement is then repeated for over a thousand iterations while shifting the droop placement to a different cycle per iteration. Silicon measurements demonstrate the DVM capability of tracking the worst case FMAX reduction to within 1% for a wide range of VCC droop profiles. Furthermore, silicon measurements reveal that FMAX is highly sensitive to the placement and magnitude of a high-frequency VCC droop during program execution, thus highlighting the value of the DVM for silicon debug. In addition, the DVM interfaces with an adaptive clock control circuit to dynamically adjust the clock frequency by changing the divide ratio in the phase-locked loop in response to persistent variations, enabling the microprocessor to adapt to the operating environment for maximum efficiency.