A Random Interrupt Dithering SAR Technique for Secure ADC Against Reference-Charge Side-Channel Attack
A Random Interrupt Dithering SAR Technique for Secure ADC Against Reference-Charge Side-Channel Attack
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DOI：
10.1109/tcsii.2019.2901534
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发表时间：
2020-01
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影响因子：
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通讯作者：
Takuji Miki;N. Miura;H. Sonoda;Kento Mizuta;M. Nagata
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文献类型：
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作者：
Takuji Miki;N. Miura;H. Sonoda;Kento Mizuta;M. Nagata
对逐次逼近寄存器（SAR）模数转换器（ADC）中的参考电荷流的侧信道攻击（SCA）公开了在传感器前端处获取的模拟信息。随机中断抖动通过注入1/4满量程的极大抖动来掩盖模拟输入和参考电荷流之间的相关性。内部抖动跟踪比较器可保证轨到轨工作，不会降低转换精度。比较器用作抖动的物理随机源。基于热噪声的比较器亚稳态操作的不可预测的随机性增强了安全级别，而比较器的共享使用减少了相关的硬件开销。该技术的额外硅面积损失仅为未受保护ADC核心面积的7%。采用0.18 μ m CMOS工艺实现了10位1 MS/s安全SAR ADC。测量结果表明，所提出的安全ADC抑制信息泄漏从4.6位到0.8位的参考电荷SCA。
A side-channel attack (SCA) on a reference-charge flow in successive approximation register (SAR) analog-to-digital converters (ADCs) discloses analog information acquired at a sensor frontend. A random interrupt dithering masks the correlation between analog input and reference charge flow by injecting extremely large dither of 1/4 full scale. An internal dither-tracking comparator yet guarantees rail-to-rail operation, resulting in no penalty in conversion accuracy. The comparator functions as a physical-random source for dithering. The unpredictable randomness based on comparator metastable operation by thermal noise enhances the security level while the shared use of the comparator reduces the associated hardware overhead. The additional silicon area penalty for the proposed technique is only 7% of an unprotected ADC core area. A 10-bit 1 MS/s secure SAR ADC was fabricated in 0.18- $\mu \text{m}$ CMOS. The measurement results demonstrate the proposed secure ADC suppresses the information leakage from 4.6 bit to 0.8 bit against reference-charge SCA.