The Art of Analog Layout
The Art of Analog Layout
复制标题
DOI：
--
复制
发表时间：
2000-12
期刊：
影响因子：
--
通讯作者：
A. Hastings
中科院分区：
文献类型：
--
作者：
A. Hastings
（注意：每章以“摘要”和“练习”结尾。）1。设备物理学。半导体。产生和重组。外部半导体。扩散和漂移。 PN连接。耗尽区域。 pH二极管。肖特基二极管。齐纳二极管。欧姆联系人。双极连接晶体管。 beta。 I-V特征。 MOS晶体管。阈值电压。 I-V特征。 JFET晶体管。 2。半导体制造。硅制造。晶体生长。晶圆制造。硅的晶体结构。光刻学。光吸毒者。光掩膜和标线。图案。氧化物的生长和去除。氧化物的生长和沉积。去除氧化物。氧化物生长和去除的其他影响。硅（Locos）的局部氧化。扩散和离子植入。扩散。扩散的其他影响。离子植入。硅沉积。外观。多硅烷沉积。金属化。沉积和去除铝。耐火屏障金属。硅化。氧化二氧化碳，二氮化物和保护性大衣。集会。安装和邦德。包装。 3。代表过程。标准双极。基本功能。制造序列。可用的设备。过程扩展。多硅栅极CMO。基本功能。制造序列。可用的设备。过程扩展。模拟bicmos。基本功能。制造序列。可用的设备。过程扩展。 4。失败机制。电力超重。静电放电（ESD）。电气移民。天线效应。污染。干腐蚀。移动离子污染。表面效应。热载体注入。寄生通道和电荷扩散。寄生虫。底物辩护。少数派载体注入。 5。电阻。电阻率和电阻性。电阻布局。电阻变异性。过程变化。温度变化。非线性。接触电阻。电阻寄生虫。可用电阻的比较。基本电阻。发射器电阻。基本捏电阻。高页面电阻。 EPI捏电阻。金属电阻。聚电阻。 NSD和PSD电阻。 N孔电阻。薄膜电阻。调整电阻值。调整电阻。修剪电阻。 6。电容器。电容。电容器变异性。过程变化。电压调制和温度变化。电容器寄生虫。可用电容器的比较。基本发射线连接电容器。 MOS电容器。多聚电容器。电容器的其他风格。 7。电阻和电容器的匹配。测量不匹配。不匹配的原因。随机统计波动。过程偏见。模式转移。多硅蚀刻速率的变化。扩散相互作用。压力梯度和包装转移。温度梯度和热电学。静电相互作用。设备匹配的规则。电阻匹配的规则。电容器匹配的规则。 8。双极晶体管。双极晶体管操作中的主题。 beta滚动。雪崩故障。热失控和次要崩溃。 NPN晶体管中的饱和度。横向PNP晶体管中的饱和度。双极晶体管的寄生虫。标准双极小信号晶体管。标准双极NPN晶体管。标准双极底物PNP晶体管。标准双极侧PNP晶体管。高压双极晶体管。替代小信号双极晶体管。标准双极的扩展。双极晶体管在CMOS过程中。高级技术双极晶体管。 9。双极晶体管的应用。功率双极晶体管。 NPN功率晶体管的故障机制。功率NPN晶体管的布局。饱和检测和限制。匹配双极晶体管。随机变化。发射极变性。 nbl阴影。热梯度。应力梯度。双极晶体管匹配的规则。匹配NPN晶体管的规则。匹配横向PNP晶体管的规则。 10。二极管。标准双极中的二极管。二极管连接的晶体管。齐纳二极管。肖特基二极管。 CMO和BICMOS过程中的二极管。匹配二极管。匹配的PN连接二极管。匹配的齐纳二极管。匹配的Schottky二极管。 11。MOS晶体管。 MOS晶体管操作中的主题。建模MOS晶体管。 MOS晶体管的寄生虫。自对准的聚根cmos晶体管。编码MOS晶体管。 N孔和P孔工艺。频道停止。阈值调整植入物。缩放晶体管。变体结构。背门触点。 12。MOS晶体管的应用。扩展的电压晶体管。 LDD和DDD晶体管。扩展的晶体管。多门氧化物。动力MOS晶体管。常规的MOS电源晶体管。 DMOS晶体管。 JFET晶体管。建模JFET。 JFET布局。 MOS晶体管匹配。几何影响。扩散和蚀刻效应。热和压力效应。 MOS晶体管的普通中央式布局。 MOS晶体管匹配规则。 13。特殊主题。合并设备。有缺陷的设备合并。成功的设备合并。低风险合并设备。中风险合并设备。设计新的合并设备。后卫戒指。标准的双极电子护罩。标准的双极孔防护戒指。 CMO和BICMOS设计中的防护戒指。单层互连。模拟布局和棍子图。交叉线索的技术。隧道的类型。构造垫圈。抄写街和对齐标记。债券，trimpad和testpads。 ESD结构。选择ESD结构。 14。组装模具。死亡计划。细胞区域估计。模具面积估计。毛利率。平面图。顶级互连。渠道路由的原理。特殊路由技术。电气移民。最小化压力效应。附录A：文本中使用的首字母缩略词表。附录B：立方晶体的米勒指数。附录C：示例布局规则。附录D：数学推导。附录E：布局编辑器软件的来源。指数。
(NOTE: Each chapter concludes with "Summary" and "Exercises.") 1. Device Physics. Semiconductors. Generation and Recombination. Extrinsic Semiconductors. Diffusion and Drift. PN Junctions. Depletion Regions. PH Diodes. Schottky Diodes. Zener Diodes. Ohmic Contacts. Bipolar Junction Transistors. Beta. I-V Characteristics. MOS Transistors. Threshold Voltage. I-V Characteristics. JFET Transistors. 2. Semiconductor Fabrication. Silicon Manufacture. Crystal Growth. Wafer Manufacturing. The Crystal Structure of Silicon. Photolithography. Photoresists. Photomasks and Reticles. Patterning. Oxide Growth and Removal. Oxide Growth and Deposition. Oxide Removal. Other Effects of Oxide Growth and Removal. Local Oxidation of Silicon (LOCOS). Diffusion and Ion Implantation. Diffusion. Other Effects of Diffusion. Ion Implantation. Silicon Deposition. Epitaxy. Polysilicon Deposition. Metallization. Deposition and Removal of Aluminum. Refractory Barrier Metal. Silicidation. Interlevel Oxide, Interlevel Nitride, and Protective Overcoat. Assembly. Mount and Bond. Packaging. 3. Representative Processes. Standard Bipolar. Essential Features. Fabrication Sequence. Available Devices. Process Extensions. Polysilicon-Gate CMOS. Essential Features. Fabrication Sequence. Available Devices. Process Extensions. Analog BiCMOS. Essential Features. Fabrication Sequence. Available Devices. Process Extensions. 4. Failure Mechanisms. Electrical Overstress. Electrostatic Discharge (ESD). Electromigration. The Antenna Effect. Contamination. Dry Corrosion. Mobile Ion Contamination. Surface Effects. Hot Carrier Injection. Parasitic Channels and Charge Spreading. Parasitics. Substrate Debiasing. Minority-Carrier Injection. 5. Resistors. Resistivity and Sheet Resistance. Resistor Layout. Resistor Variability. Process Variation. Temperature Variation. Nonlinearity. Contact Resistance. Resistor Parasitics. Comparison of Available Resistors. Base Resistors. Emitter Resistors. Base Pinch Resistors. High-Sheet Resistors. Epi Pinch Resistors. Metal Resistors. Poly Resistors. NSD and PSD Resistors. N-Well Resistors. Thin-Film Resistors. Adjusting Resistor Values. Tweaking Resistors. Trimming Resistors. 6. Capacitors. Capacitance. Capacitor Variability. Process Variation. Voltage Modulation and Temperature Variation. Capacitor Parasitics. Comparison of Available Capacitors. Base-Emitter Junction Capacitors. MOS Capacitors. Poly-Poly Capacitors. Miscellaneous Styles of Capacitors. 7. Matching of Resistors and Capacitors. Measuring Mismatch. Causes of Mismatch. Random Statistical Fluctuations. Process Biases. Pattern Shift. Variations in Polysilicon Etch Rate. Diffusion Interactions. Stress Gradients and Package Shifts. Temperature Gradients and Thermoelectrics. Electrostatic Interactions. Rules for Device Matching. Rules for Resistor Matching. Rules for Capacitor Matching. 8. Bipolar Transistors. Topics in Bipolar Transistor Operation. Beta Rolloff. Avalanche Breakdown. Thermal Runaway and Secondary Breakdown. Saturation in NPN Transistors. Saturation in Lateral PNP Transistors. Parasitics of Bipolar Transistors. Standard Bipolar Small-Signal Transistors. The Standard Bipolar NPN Transistor. The Standard Bipolar Substrate PNP Transistor. The Standard Bipolar Lateral PNP Transistor. High-Voltage Bipolar Transistors. Alternative Small-Signal Bipolar Transistors. Extensions to Standard Bipolar. Bipolar Transistors in a CMOS Process. Advanced-Technology Bipolar Transistors. 9. Applications of Bipolar Transistors. Power Bipolar Transistors. Failure Mechanisms of NPN Power Transistors. Layout of Power NPN Transistors. Saturation Detection and Limiting. Matching Bipolar Transistors. Random Variations. Emitter Degeneration. NBL Shadow. Thermal Gradients. Stress Gradients. Rules for Bipolar Transistor Matching. Rules for Matching NPN Transistors. Rules for Matching Lateral PNP Transistors. 10. Diodes. Diodes in Standard Bipolar. Diode-Connected Transistors. Zener Diodes. Schottky Diodes. Diodes in CMOS and BiCMOS Processes. Matching Diodes. Matching PN Junction Diodes. Matching Zener Diodes. Matching Schottky Diodes. 11. MOS Transistors. Topics in MOS Transistor Operation. Modeling the MOS Transistor. Parasitics of MOS Transistors. Self-Aligned Poly-Gate CMOS Transistors. Coding the MOS Transistor. N-Well and P-Well Processes. Channel Stops. Threshold Adjust Implants. Scaling the Transistor. Variant Structures. Backgate Contacts. 12. Applications of MOS Transistors. Extended-Voltage Transistors. LDD and DDD Transistors. Extended-Drain Transistors. Multiple Gate Oxides. Power MOS Transistors. Conventional MOS Power Transistors. DMOS Transistors. The JFET Transistor. Modeling the JFET. JFET Layout. MOS Transistor Matching. Geometric Effects. Diffusion and Etch Effects. Thermal and Stress Effects. Common-Centroid Layout of MOS Transistors. Rules for MOS Transistor Matching. 13. Special Topics. Merged Devices. Flawed Device Mergers. Successful Device Mergers. Low-Risk Merged Devices. Medium-Risk Merged Devices. Devising New Merged Devices. Guard Rings. Standard Bipolar Electron Guard Rings. Standard Bipolar Hole Guard Rings. Guard Rings in CMOS and BiCMOS Designs. Single-Level Interconnection. Mock Layouts and Stick Diagrams. Techniques for Crossing Leads. Types of Tunnels. Constructing the Padring. Scribe Streets and Alignment Markers. Bondpads, Trimpads, and Testpads. ESD Structures. Selecting ESD Structures. 14. Assembling the Die. Die Planning. Cell Area Estimation. Die Area Estimation. Gross Profit Margin. Floorplanning. Top-Level Interconnection. Principles of Channel Routing. Special Routing Techniques. Electromigration. Minimizing Stress Effects. Appendix A: Table of Acronyms Used in the Text. Appendix B: The Miller Indices of a Cubic Crystal. Appendix C: Sample Layout Rules. Appendix D: Mathematical Derivations. Appendix E: Sources for Layout Editor Software. Index.