Cooperative prefetching: compiler and hardware support for effective instruction prefetching in modern processors
Cooperative prefetching: compiler and hardware support for effective instruction prefetching in modern processors
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协作预取：现代处理器中有效指令预取的编译器和硬件支持
DOI：
10.1109/micro.1998.742780
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发表时间：
1998
期刊：
影响因子：
--
通讯作者：
T. Mowry
中科院分区：
文献类型：
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作者：
C. Luk;T. Mowry
指示缓存延迟延迟已成为越来越重要的性能瓶颈，尤其是对于商业应用。尽管预拿教学是一种容忍这种潜伏期的有吸引力的技术，但我们发现现有的预取方案不足以使现代超级处理器足够及早发布预取，尤其是对于非序列访问）。为了克服这些限制，我们提出了一种新的指令预取技术，硬件和软件可以合作以如下所示隐藏延迟。硬件执行具有侵略性的顺序预取，并结合了一种新型的预取滤器机制，可以使其在不污染缓存的情况下取得领先地位。为了隐藏非序列访问的延迟，我们提出并实现了一种新颖的编译器算法，该算法会自动将指令预取指令插入可执行文件中，以预摘要控制的目标提前足够远。我们的实验结果表明，这种新方法导致在原始执行时间内的速度从9.4％到18.5％至18.5％（平均13.3％）。这是最佳现有方案的平均速度（6.5％）的两倍以上。这是通过平均隐藏原始说明失速时间的71％来实现的，而现有最佳方案仅为36％。我们发现，我们设计的预取过滤和编译器插入的预取组件都是必不可少的和互补的，即编译器可以平均将代码扩展限制为少于10％，而且我们的方案在遗迹延迟的变化方面是可靠的和带宽。
Instruction cache miss latency is becoming an increasingly important performance bottleneck, especially for commercial applications. Although instruction prefetching is an attractive technique for tolerating this latency, we find that existing prefetching schemes are insufficient for modern superscalar processors since they fail to issue prefetches early enough (particularly for non-sequential accesses). To overcome these limitations, we propose a new instruction prefetching technique whereby the hardware and software cooperate to hide the latency as follows. The hardware performs aggressive sequential prefetching combined with a novel prefetch filtering mechanism to allow it to get far ahead without polluting the cache. To hide the latency of non-sequential accesses, we propose and implement a novel compiler algorithm which automatically inserts instruction prefetch instructions into the executable to prefetch the targets of control transfers far enough in advance. Our experimental results demonstrate that this new approach results in speedups ranging from 9.4% to 18.5% (13.3% on average) over the original execution time on an out-of-order superscalar processor; which is more than double the average speedup of the best existing schemes (6.5%). This is accomplished by hiding an average of 71% of the original instruction stall time, compared with only 36% for the best existing schemes. We find that both the prefetch filtering and compiler-inserted prefetching components of our design are essential and complementary, that the compiler can limit the code expansion to less than 10% on average, and that our scheme is robust with respect to variations in miss latency and bandwidth.