A 23 mW 256-tap 8 MSample/s QPSK matched filter for DS-CDMA cellular telephony using recycling integrator correlators
A 23 mW 256-tap 8 MSample/s QPSK matched filter for DS-CDMA cellular telephony using recycling integrator correlators
复制标题
用于 DS-CDMA 蜂窝电话的 23 mW 256 抽头 8 MSample/s QPSK 匹配滤波器，使用循环积分器相关器
DOI：
10.1109/isscc.2000.839813
复制
发表时间：
2000
期刊：
影响因子：
--
通讯作者：
K. Iizuka
中科院分区：
文献类型：
--
作者：
D. Senderowicz;S. Azuma;H. Matsui;K. Hara;S. Kawama;Y. Ohta;M. Miyamoto;K. Iizuka
在直接序列码分多址（DS-CDMA）中，匹配滤波器计算由伪随机噪声（PN）序列和复制PN序列扩展的接收信号的互相关函数。这样的匹配滤波器可以看作是一个有限脉冲响应（FIR）滤波器，PN序列用作二进制抽头权重，最小化DS-CDMA接收机中的搜索和同步时间。本文介绍了一种基于循环积分器（RIC）实现匹配滤波器的方法，该方法使用模拟和数字处理的合理组合，以最大限度地减少面积和功耗。匹配滤波器由RIC阵列、存储PN序列的循环移位寄存器和逐个传输相关值的旋转多路复用器组成。该实现提供：1）不需要快速ADC的输入模拟信号处理能力; 2）已经数字编码的输出流; 3）用于开关电容器（SC）积分器的小电容器比;以及4）用于可用技术和扩频比（即PN序列的长度）的最小管芯面积和电流消耗。制作工艺采用0.35 /spl μ/m CMOS双金属双多晶硅工艺。该芯片的面积为22.8 mm/sup 2/，功耗为23 mW，采用1.8 V电源供电。
In direct sequence code division multiple access (DS-CDMA), matched filters calculate the cross-correlation function of a received signal spread by a pseudo-random noise (PN) sequence and a replica PN sequence. A matched filter like this can be viewed as a finite impulse response (FIR) filter with a PN sequence used as the binary tap weights, minimizing search and synchronization times in DS-CDMA receivers. This paper introduces an approach for implementing matched filters based on recycling integrator correlators (RICs) that use a sensible combination of analog and digital processing to minimize area and power consumption. The matched filter is organized by combining an array of RICs, a cyclic shift register which stores a PN sequence, and a rotary multiplexer which transfers the correlation values one by one. This implementation provides: 1) an input analog signal processing capability without the need of a fast ADC; 2) an already digitally-coded output stream; 3) small capacitor ratios for the switched-capacitor (SC) integrators; and 4) minimum die-area and current consumption for the available technology and the spreading ratio, that is, the length of the PN sequence. The fabrication process is a 0.35 /spl mu/m CMOS double-metal, double-poly process. The chip occupies 22.8 mm/sup 2/ and dissipates 23 mW with a 1.8 V power supply.