Evaluation of the CAESAR hardware API for lightweight implementations
Evaluation of the CAESAR hardware API for lightweight implementations
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DOI：
10.1109/reconfig.2017.8279790
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发表时间：
2017-12
期刊：
影响因子：
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通讯作者：
Panasayya Yalla;J. Kaps
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文献类型：
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作者：
Panasayya Yalla;J. Kaps
认证加密竞赛：安全性、适用性和鲁棒性（CAESAR）要求候选算法的所有硬件实现都遵守CAESAR硬件API [1]。CAESAR硬件API由一个开发包支持，该开发包包括用于高速通用预处理器和后处理器的VHDL代码，最近还用于轻量级实现。这些处理器被设计成使密码核心与API兼容。然而，对于轻量级实现，通常假设具有通用的预处理器和后处理器增加了将其功能与密码核心合并的面积消耗。在本文中，我们通过两个案例研究来评估轻量级包。首先，我们验证了轻量级封装比高速封装具有更小的占地面积。其次，我们表明，使用通用的轻量级的前处理器和后处理器的开销，将其功能集成到密码核心是可以忽略不计的。作为这些案例研究的一部分，我们开发了Ketje-Sr、Ascon-128和Ascon-128 a的第一个轻量级实现。
The Competition for Authenticated Encryption: Security, Applicability, and Robustness (CAESAR) requires that all hardware implementations of candidate algorithms adhere to the CAESAR Hardware API [1]. The CAESAR Hardware API is supported by a development package which includes VHDL code for universal pre- and post-processors for high-speed and recently also for lightweight implementations. These processors are designed to make a cipher core compliant with the API. However, for lightweight implementations it is generally assumed that having generic pre- and post-processors increases the area consumption over merging their functionality with the cipher cores. In this paper we evaluate the lightweight package through two case studies. First, we verified that the lightweight package has a smaller area footprint than the high-speed package. Second, we show that the overhead of using the generic lightweight pre- and post-processors over integrating their functionality into the cipher core is negligible. As part of these case studies, we have developed the first lightweight implementations of Ketje-Sr, Ascon-128, and Ascon-128a.