An enhanced power integrity analysis flow based on the interdependence between simultaneous switching output noise and static IR drop
An enhanced power integrity analysis flow based on the interdependence between simultaneous switching output noise and static IR drop
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DOI：
10.1109/ectc.2014.6897340
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发表时间：
2014-05
期刊：
影响因子：
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通讯作者：
Minghui Han;A. Amirkhany;Wei Xiong
中科院分区：
文献类型：
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作者：
Minghui Han;A. Amirkhany;Wei Xiong
本文深入研究了片上电源栅极电阻对同步开关输出（SSO）噪声的影响。该研究的一个关键观察结果是，在某些情况下，增加供电电网某些部分的电阻可以非常有效地降低SSO噪声，并且SSO噪声降低的增益可以显著超过静态IR降的增加。基于这一观察结果，提出了一种用于高速接口设计的增强型电源完整性分析流程。与传统的做法不同，我们提出的流程认为SSO噪声和静态IR降作为两个密切相关的问题，并在整个设计过程中的协同设计的方式来解决它们。
This paper presents an in-depth study on how the magnitude of simultaneous switching output (SSO) noise is affected by on-chip supply grid resistances. A key observation of the study is that under certain circumstances, increasing the resistance of certain parts of a supply grid can be very effective in reducing SSO noise, and the gain from SSO noise reduction can significantly outweigh the resulted increase in static IR drop. Based on this observation, an enhanced power integrity analysis flow is proposed for high speed interface design. Unlike conventional practices, our proposed flow considers SSO noise and static IR drop as two closely interrelated issues, and addresses them in a co-design manner throughout the design process.