VHDL implementation of self-timed 32-bit floating point multiplier with carry look ahead adder
VHDL implementation of self-timed 32-bit floating point multiplier with carry look ahead adder
复制标题
带进位先行加法器的自定时 32 位浮点乘法器的 VHDL 实现
DOI：
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发表时间：
2016
期刊：
影响因子：
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通讯作者：
S. Nemade
中科院分区：
文献类型：
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作者：
Salty Beohar;S. Nemade
大量的计算机应用程序（如计算机图形学，控制系统，建模系统，模拟器等）需要浮点运算。然而，大多数目前可用的方法是缓慢和低效的，因为顺序设计，但在可编程逻辑器件领域，如FPLA和CPLD的最新发展开辟了并行和高速浮点设计的新领域。考虑到同步架构要求所有时钟事件在整个电路上同时发生，这是不可能的，由于时钟偏斜，电路的延迟和吞吐量也直接与最慢元件的最坏情况延迟相关，这增加了延迟。因此，本文提出了自定时超前进位加法器的基础上实现的IEEE 754 32位浮点乘法器的FPGA器件。仿真结果表明，该设计比同步设计具有更低的延迟以及更低的功耗要求。
A large number of computer applications(like Computer Graphics, Control Systems, Modeling System, Simulators etc.) needed floating point arithmetic. However, most of the presently available methods are slow and inefficient because of sequential design however the recent development in the field of programmable logic devices such as FPLA and CPLD opens the new area of parallel and high speed floating point designs. Considering that the synchronous architectures requires that that all clock events happen at the same time over the complete circuit which it not possible due to clock skew also the latency and throughput of the circuit are directly linked to the worst-case delay of the slowest element which increases the delay. Hence this paper presents self-timed carry look ahead adder based implementation of IEEE 754 32 bit floating point multiplier for FPGA devices. The simulation results shows that the proposed design has lower latency than synchronous design as well as lower power requirements.