A Fast Integral Image Computing Hardware Architecture With High Power and Area Efficiency
A Fast Integral Image Computing Hardware Architecture With High Power and Area Efficiency
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DOI：
10.1109/tcsii.2014.2362651
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发表时间：
2015-01
期刊：
影响因子：
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通讯作者：
P. Ouyang;Shouyi Yin;Yuchi Zhang;Leibo Liu;Shaojun Wei
中科院分区：
文献类型：
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作者：
P. Ouyang;Shouyi Yin;Yuchi Zhang;Leibo Liu;Shaojun Wei
积分图像计算是许多视觉应用的重要组成部分，具有计算密集和频繁访问内存的特点。本简报提出了一种具有高面积和功率效率的快速积分图像计算方法。针对积分图像计算的数据流，提出了一种面向双向数据的积分图像计算机制以提高处理效率，并设计了一种支持该机制的流水线并行结构。分析了该方法的并行性和时间复杂度，并给出了该结构的硬件实现代价。与现有的方法相比，该架构以较低的逻辑资源和功耗实现了最高的处理速度。
Integral image computing is an important part of many vision applications and is characterized by intensive computation and frequent memory accessing. This brief proposes an approach for fast integral image computing with high area and power efficiency. For the data flow of the integral image computation a dual-direction data-oriented integral image computing mechanism is proposed to improve the processing efficiency, and then a pipelined parallel architecture is designed to support this mechanism. The parallelism and time complexity of the approach are analyzed and the hardware implementation cost of the proposed architecture is also presented. Compared with the state-of-the-art methods this architecture achieves the highest processing speed with comparatively low logic resources and power consumption.