Impact of power-supply noise on timing in high-frequency microprocessors
Impact of power-supply noise on timing in high-frequency microprocessors
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DOI：
10.1109/epep.2002.1057928
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发表时间：
2004
影响因子：
--
通讯作者：
M. Saint-Laurent;M. Swaminathan
中科院分区：
文献类型：
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作者：
M. Saint-Laurent;M. Swaminathan
本文分析了电源噪声对高频微处理器性能的影响。首先，延迟模型，考虑到这种噪声提出了设备为主和互连为主的定时路径。对于典型的电路，它示出的噪声的峰值在很大程度上是无关紧要的，并且在切换过程中的平均电源电压是更重要的。然后，有人认为，全球差分噪声可能有一个更大的时序影响比共模噪声。最后，现实值的模型参数测量2.53 GHz的奔腾4微处理器使用130纳米技术。这些值意味着系统主板上的电源噪声使时钟频率降低了6.7%。该模型表明，与此电源噪声相关的频率损失将稳步增加，并在90 nm技术世代达到7.6%。
This paper analyzes the impact of power-supply noise on the performance of high-frequency microprocessors. First, delay models that take this noise into account are proposed for device-dominated and interconnect-dominated timing paths. For typical circuits, it is shown that the peak of the noise is largely irrelevant and that the average supply voltage during switching is more important. It is then argued that global differential noise can potentially have a greater timing impact than common-mode noise. Finally, realistic values for the model parameters are measured on a 2.53-GHz Pentium4 microprocessor using a 130-nm technology. These values imply that the power-supply noise present on the system board reduces clock frequency by 6.7%. The model suggests that the frequency penalty associated with this power-supply noise will steadily increase and reach 7.6% for the 90-nm technology generation.