Discrete domain modeling of an all-digital frequency locked loop
Discrete domain modeling of an all-digital frequency locked loop
复制标题
全数字锁频环的离散域建模
DOI：
10.1109/smicnd.2017.8101214
复制
发表时间：
2017
期刊：
影响因子：
--
通讯作者：
Marina Dana Topa
中科院分区：
文献类型：
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作者：
E. Szopos;I. Saracut;B. Kirei;Marina Dana Topa
在本文中，一个全数字频率锁定环-这是由一个数控振荡器，计数器和锁存器（与频率检测的范围）和累加器的控制回路-在z域建模考虑两个显着的误差源，发生在其结构：有限的分辨率的数字信号和频率检测的不准确性。开发的离散时间模型在LabVIEW中实现，并与Verilog中实现的锁频环的结构描述进行了比较。给出了8、10和12位分辨率数控振荡器的仿真结果。采用低分辨率的数控振荡器可以在更短的时间内实现频率锁定，但抖动性能最差。如果使用更高的分辨率，则可以以更高的频率锁定时间为代价来改善抖动。峰峰值抖动性能与数控振荡器分辨率的关系曲线有助于确定所需抖动的最小值。
In this paper an all-digital frequency locked loop — which is composed of a digitally controlled oscillator, a counter and a latch (with the scope of frequency detection) and an accumulator in the control loop — is modeled in the z-domain considering two significant error sources that occur in its structure: the finite resolution of the digital signals and the inaccuracy of the frequency detection. The developed discrete time model was implemented in LabVIEW and it was compared against a structural description of the frequency locked loop achieved in Verilog. Simulation results for digitally controlled oscillator with 8, 10 and 12 bits resolution were obtained for both models. Employing a low resolution digitally controlled oscillator the loop can achieve frequency lock in less time, but its jitter performance is worst. The jitter can be improved if higher resolution is used, at the cost of a higher frequency lock time. The peak-to-peak jitter performance was plotted against the resolution of the digitally controlled oscillator that is helpful to determine the minimum for a desiredjitter.