Design and Implementation of Ultra-Small-Size and Ultra-Low-Power Digital Systems on GaAs-based Hexagonal Nanowire Networks Utilizing a Hexagonal BDD Quantum Circuit Approach
Design and Implementation of Ultra-Small-Size and Ultra-Low-Power Digital Systems on GaAs-based Hexagonal Nanowire Networks Utilizing a Hexagonal BDD Quantum Circuit Approach
复制标题
利用六角 BDD 量子电路方法在砷化镓基六角纳米线网络上设计和实现超小尺寸和超低功耗数字系统
DOI：
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发表时间：
2004
期刊：
影响因子：
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通讯作者：
H. Hasegawa
中科院分区：
文献类型：
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作者：
S. Kasai;M. Yumoto;T. Sato;H. Hasegawa
This paper discusses feasibility of design and future implementation of ultra-small-size and ultra-low-power digital logic systems by a hexagonal BDD (binary-decision diagram) quantum circuit approach. The discussion is based on various circuits formed on GaAs-based hexagonal nanowire networks controlled by nanometer scale Schottky wrap gates (WPGs). Starting from basic node devices and elementary logic function blocks, fabrication technology of hexagonal BDD quantum circuits up to 8-bit adders with node densities over 45 million nodes/cm 2 has been successfully developed. Their correct operations at low temperatures and room temperature have been confirmed by experiments and simulation. Various circuit components in logic processors, including arithmetic logic unit (ALU), controller and decoders have been successfully designed as hexagonal BDD layouts without nanowire crossover. For sequential circuits, WPG-controlled nanowire FETs on hexagonal networks have been investigated, and registers and counters have been implemented using these nanowire FETs showing correct operation. Hexagonal BDD-based static 2-bit nano-processor unit (NPU) has been successfully designed completely on hexagonal nanowire network. Ultra high-density GaAs hexagonal nanowire networks with much smaller wire sizes than those of etched nanowire networks have been successfully formed by selective MBE growth, showing great promise for room temperature operation in quantum regime as well as reduction of system area and power consumption.
