Exploring Portability and Performance of OpenCL FPGA Kernels on Intel HARPv2
Exploring Portability and Performance of OpenCL FPGA Kernels on Intel HARPv2
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DOI：
10.1145/3318170.3318180
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发表时间：
2019-05
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通讯作者：
A. Cabrera;R. Chamberlain
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文献类型：
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作者：
A. Cabrera;R. Chamberlain
FPGA 提供了异构计算解决方案，通过创建加速计算的专用硬件来满足对提高性能的持续需求。虽然进入门槛历来很高，但高级综合 (HLS) 的进步使 FPGA 变得更容易使用。具体来说，英特尔 FPGA OpenCL SDK 允许软件设计人员抽象出 FPGA 上硬件架构的低级细节，并允许他们用更高级的语言编写计算内核。此外，英特尔还开发了一种系统，将多核 Xeon CPU 和 Arria 10 FPGA 整合到同一个芯片封装中，作为异构加速器研究计划 (HARP) 的一部分，该计划可以作为其 SDK 的目标。在这项工作中，我们的目标是通过移植最初为通过 PCIe 总线连接的 FPGA 编写的 OpenCL 内核，使用 HLS 实现 HARP 平台 (HARPv2) 的第二次迭代。我们根据之前报告的结果评估 HARPv2 系统的性能，通过硬件设计空间搜索探索内核的可移植性，并凭经验展示使用共享虚拟内存 (SVM) 抽象相对于显式读写的好处。
FPGAs offer a heterogenous compute solution to the continuous desire for increased performance by enabling the creation of application-specific hardware that accelerates computation. While the barrier to entry has historically been steep, advances in High Level Synthesis (HLS) are making FPGAs more accessible. Specifically, the Intel FPGA OpenCL SDK allows software designers to abstract away low level details of architecting hardware on an FPGA and allows them to author computational kernels in a higher level language. Furthermore, Intel has developed a system that incorporates both a multicore Xeon CPU and Arria 10 FPGA into the same chip package as part of the Heterogeneous Accelerator Research Program (HARP) that can be targeted by their SDK. In this work, we target the second iteration of the HARP platform (HARPv2) using HLS through porting of OpenCL kernels originally written for FPGAs connected via a PCIe bus. We evaluate the HARPv2 system's performance against previously reported results, explore the portability of kernels through a hardware design space search, and empirically show the benefits of using the shared virtual memory (SVM) abstraction over explicit reads and writes.